From 321254cc389bf458695e0fe934a37e55d7342a3f Mon Sep 17 00:00:00 2001 From: Gwenhael Goavec-Merou Date: Mon, 30 Oct 2023 11:14:30 +0100 Subject: [PATCH] soc/integration/soc: pass bus.address_width to UARTBone constructor --- litex/soc/integration/soc.py | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index 3fd236338..7e5588658 100644 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -1481,7 +1481,11 @@ class LiteXSoC(SoC): clk_freq = self.sys_clk_freq self.check_if_exists(name) uartbone_phy = uart.UARTPHY(self.platform.request(uart_name), clk_freq, baudrate) - uartbone = uart.UARTBone(phy=uartbone_phy, clk_freq=clk_freq, cd=cd) + uartbone = uart.UARTBone( + phy = uartbone_phy, + clk_freq = clk_freq, + cd = cd, + addr_width = self.bus.address_width) self.add_module(name=f"{name}_phy", module=uartbone_phy) self.add_module(name=name, module=uartbone) self.bus.add_master(name=name, master=uartbone.wishbone)