From 321dd8fcf6586bc88806cae61f1538756cde8eb4 Mon Sep 17 00:00:00 2001 From: David Shah Date: Fri, 22 Feb 2019 12:12:10 +0000 Subject: [PATCH] versa_ecp5: Remove negative diff IO pins In Lattice FPGAs only the positive side of differential pairs should be specified (unlike Xilinx) These are a warning on Diamond (which trims unused IO) and an error with Yosys/nextpnr (which doesn't so they conflict when the positive pin is 'expanded'). Already this is the case for the clock input, this commit performs the same change for the DDR3 pins. --- litex/boards/platforms/versa_ecp5.py | 2 -- 1 file changed, 2 deletions(-) diff --git a/litex/boards/platforms/versa_ecp5.py b/litex/boards/platforms/versa_ecp5.py index dbfc26cf5..7d11e4702 100644 --- a/litex/boards/platforms/versa_ecp5.py +++ b/litex/boards/platforms/versa_ecp5.py @@ -50,9 +50,7 @@ _io = [ IOStandard("SSTL135_I"), Misc("TERMINATION=75")), Subsignal("dqs_p", Pins("K2 H4"), IOStandard("SSTL135D_I"), Misc("TERMINATION=OFF"), Misc("DIFFRESISTOR=100")), - Subsignal("dqs_n", Pins("J1 G5"), IOStandard("SSTL135D_I")), Subsignal("clk_p", Pins("M4"), IOStandard("SSTL135D_I")), - Subsignal("clk_n", Pins("N5"), IOStandard("SSTL135D_I")), Subsignal("cke", Pins("N2"), IOStandard("SSTL135_I")), Subsignal("odt", Pins("L2"), IOStandard("SSTL135_I")), Subsignal("reset_n", Pins("N4"), IOStandard("SSTL135_I")),