From 32676fffd22b7b1c3cfaf7ed2baff1baa9200c51 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Fri, 13 Mar 2015 23:19:08 +0100 Subject: [PATCH] soc/sdram: sync with new mibuild toolchain management --- misoclib/soc/sdram.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/misoclib/soc/sdram.py b/misoclib/soc/sdram.py index e9fbca152..e6ecb9304 100644 --- a/misoclib/soc/sdram.py +++ b/misoclib/soc/sdram.py @@ -53,8 +53,8 @@ class SDRAMSoC(SoC): # XXX Vivado 2014.X workaround, Vivado is not able to map correctly our L2 cache. # Issue is reported to Xilinx and should be fixed in next releases (2015.1?). # Remove this workaround when fixed by Xilinx. - from mibuild.xilinx.vivado import XilinxVivadoPlatform - if isinstance(self.platform, XilinxVivadoPlatform): + from mibuild.xilinx.vivado import XilinxVivadoToolchain + if isinstance(self.platform.toolchain, XilinxVivadoToolchain): from migen.fhdl.simplify import FullMemoryWE self.submodules.wishbone2lasmi = FullMemoryWE(wishbone2lasmi.WB2LASMI(self.l2_size//4, self.sdram.crossbar.get_master())) else: