diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py
index 50feab0ba..5af8f55fb 100644
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@@ -148,7 +148,8 @@ class SoCCore(Module):
                 self.submodules.uart  = uart.UARTStub()
             else:
                 self.submodules.uart_phy = uart.RS232PHY(platform.request(uart_name), clk_freq, uart_baudrate)
-                self.submodules.uart = uart.UART(self.uart_phy)
+                self.submodules.uart = ResetInserter()(uart.UART(self.uart_phy))
+
         #else:
         #    del self.soc_interrupt_map["uart"]