From 32d5a751db2395b2d26ac4334b63212d7154c24b Mon Sep 17 00:00:00 2001 From: Sean Cross Date: Thu, 5 Jul 2018 16:56:13 +0800 Subject: [PATCH] soc_core: uart: add a reset line to the UART Enable resetting the UART by adding a ResetInserter to the UART. The UART must be reset when resetting the softcore. Signed-off-by: Sean Cross --- litex/soc/integration/soc_core.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py index 50feab0ba..5af8f55fb 100644 --- a/litex/soc/integration/soc_core.py +++ b/litex/soc/integration/soc_core.py @@ -148,7 +148,8 @@ class SoCCore(Module): self.submodules.uart = uart.UARTStub() else: self.submodules.uart_phy = uart.RS232PHY(platform.request(uart_name), clk_freq, uart_baudrate) - self.submodules.uart = uart.UART(self.uart_phy) + self.submodules.uart = ResetInserter()(uart.UART(self.uart_phy)) + #else: # del self.soc_interrupt_map["uart"]