From 32dc99ebe0cd342e18a15327f60b5b29db5fbc15 Mon Sep 17 00:00:00 2001 From: Jevin Sweval Date: Mon, 23 May 2022 12:09:27 -0700 Subject: [PATCH] ClockFrequency(cd_or_sig, set_freq=None) to get/set the frequency of a domain or signal --- litex/soc/cores/clock/common.py | 15 +++++++++++++++ litex/soc/cores/clock/intel_common.py | 3 +++ 2 files changed, 18 insertions(+) diff --git a/litex/soc/cores/clock/common.py b/litex/soc/cores/clock/common.py index 1dda879bf..33a19a8ad 100644 --- a/litex/soc/cores/clock/common.py +++ b/litex/soc/cores/clock/common.py @@ -8,6 +8,7 @@ import logging import math from migen import Record +from migen.fhdl.structure import ClockDomain from litex.soc.integration.soc import colorer @@ -56,3 +57,17 @@ def clkdiv_range(start, stop, step=1): while current < stop: yield int(current) if math.floor(current) == current else current current += step + +def ClockFrequency(cd_or_signal="sys", set_freq=None): + CF = ClockFrequency + CF.freqs = getattr(CF, 'freqs', {}) + if set_freq is not None: + if isinstance(cd_or_signal, ClockDomain): + CF.freqs[cd_or_signal.name] = set_freq + else: + CF.freqs[cd_or_signal] = set_freq + else: + try: + return CF.freqs[cd_or_signal] + except KeyError: + raise KeyError(f"ClockFrequency has not yet been set for domain/signal '{cd_or_signal}'") diff --git a/litex/soc/cores/clock/intel_common.py b/litex/soc/cores/clock/intel_common.py index 6a0be5382..0fb813ca8 100644 --- a/litex/soc/cores/clock/intel_common.py +++ b/litex/soc/cores/clock/intel_common.py @@ -36,6 +36,7 @@ class IntelClocking(Module, AutoCSR): else: raise ValueError self.clkin_freq = freq + ClockFrequency(clkin, set_freq=freq) register_clkin_log(self.logger, clkin, freq) def create_clkout(self, cd, freq, phase=0, margin=1e-2, with_reset=True): @@ -45,6 +46,8 @@ class IntelClocking(Module, AutoCSR): if with_reset: self.specials += AsyncResetSynchronizer(cd, ~self.locked) self.comb += cd.clk.eq(clkout) + ClockFrequency(cd, set_freq=freq) + ClockFrequency(clkout, set_freq=freq) create_clkout_log(self.logger, cd.name, freq, margin, self.nclkouts) self.nclkouts += 1