From 3346bf8b2b918d56da5e88d91ae9582d2cb5f968 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 22 Jan 2015 10:45:11 +0100 Subject: [PATCH] frontend: simplify --- litesata/__init__.py | 4 +-- litesata/frontend/arbiter.py | 47 ++++++++++++++++------------------- litesata/frontend/bist.py | 12 ++++----- litesata/frontend/common.py | 4 +++ litesata/frontend/crossbar.py | 18 ++++++-------- litesata/test/bist_tb.py | 2 +- make.py | 11 +++----- targets/bist.py | 2 +- targets/core.py | 11 ++++---- 9 files changed, 52 insertions(+), 59 deletions(-) diff --git a/litesata/__init__.py b/litesata/__init__.py index 78c3a8ca6..d3f86a55b 100644 --- a/litesata/__init__.py +++ b/litesata/__init__.py @@ -7,7 +7,6 @@ from migen.bank.description import * class LiteSATA(Module, AutoCSR): def __init__(self, phy, buffer_depth=2*fis_max_dwords, - with_crossbar=False, with_bist=False, with_bist_csr=False): # phy self.phy = phy @@ -16,8 +15,7 @@ class LiteSATA(Module, AutoCSR): self.core = LiteSATACore(self.phy, buffer_depth) # frontend - if with_crossbar: - self.crossbar = LiteSATACrossbar(self.core) + self.crossbar = LiteSATACrossbar(self.core) if with_bist: self.bist = LiteSATABIST(self.crossbar, with_bist_csr) diff --git a/litesata/frontend/arbiter.py b/litesata/frontend/arbiter.py index 049946c16..73eafaa31 100644 --- a/litesata/frontend/arbiter.py +++ b/litesata/frontend/arbiter.py @@ -4,28 +4,25 @@ from litesata.frontend.common import * from migen.genlib.roundrobin import * class LiteSATAArbiter(Module): - def __init__(self, slaves, master): - if len(slaves) == 1: - self.comb += slaves[0].connect(master) - else: - self.rr = RoundRobin(len(slaves)) - self.grant = self.rr.grant - cases = {} - for i, slave in enumerate(slaves): - sink, source = slave.sink, slave.source - start = Signal() - done = Signal() - ongoing = Signal() - self.comb += [ - start.eq(sink.stb & sink.sop), - done.eq(source.stb & source.last & source.eop & source.ack) - ] - self.sync += \ - If(start, - ongoing.eq(1) - ).Elif(done, - ongoing.eq(0) - ) - self.comb += self.rr.request[i].eq((start | ongoing) & ~done) - cases[i] = [slaves[i].connect(master)] - self.comb += Case(self.grant, cases) + def __init__(self, users, master): + self.rr = RoundRobin(len(users)) + self.grant = self.rr.grant + cases = {} + for i, slave in enumerate(users): + sink, source = slave.sink, slave.source + start = Signal() + done = Signal() + ongoing = Signal() + self.comb += [ + start.eq(sink.stb & sink.sop), + done.eq(source.stb & source.last & source.eop & source.ack) + ] + self.sync += \ + If(start, + ongoing.eq(1) + ).Elif(done, + ongoing.eq(0) + ) + self.comb += self.rr.request[i].eq((start | ongoing) & ~done) + cases[i] = [users[i].connect(master)] + self.comb += Case(self.grant, cases) diff --git a/litesata/frontend/bist.py b/litesata/frontend/bist.py index e34e71bcd..ae6d2999c 100644 --- a/litesata/frontend/bist.py +++ b/litesata/frontend/bist.py @@ -5,7 +5,7 @@ from migen.fhdl.decorators import ModuleDecorator from migen.bank.description import * class LiteSATABISTGenerator(Module): - def __init__(self, sata_master_port): + def __init__(self, user_port): self.start = Signal() self.sector = Signal(48) self.count = Signal(16) @@ -17,7 +17,7 @@ class LiteSATABISTGenerator(Module): ### - source, sink = sata_master_port.source, sata_master_port.sink + source, sink = user_port.sink, user_port.source self.counter = counter = Counter(bits_sign=32) @@ -65,7 +65,7 @@ class LiteSATABISTGenerator(Module): self.sync += If(sink.stb & sink.ack, self.aborted.eq(sink.failed)) class LiteSATABISTChecker(Module): - def __init__(self, sata_master_port): + def __init__(self, user_port): self.start = Signal() self.sector = Signal(48) self.count = Signal(16) @@ -77,7 +77,7 @@ class LiteSATABISTChecker(Module): ### - source, sink = sata_master_port.source, sata_master_port.sink + source, sink = user_port.sink, user_port.source self.counter = counter = Counter(bits_sign=32) self.error_counter = Counter(self.errors, bits_sign=32) @@ -204,7 +204,7 @@ class LiteSATABISTUnitCSR(Module, AutoCSR): ] class LiteSATABISTIdentify(Module): - def __init__(self, sata_master_port): + def __init__(self, user_port): self.start = Signal() self.done = Signal() @@ -213,7 +213,7 @@ class LiteSATABISTIdentify(Module): ### - source, sink = sata_master_port.source, sata_master_port.sink + source, sink = user_port.sink, user_port.source self.fsm = fsm = FSM(reset_state="IDLE") fsm.act("IDLE", diff --git a/litesata/frontend/common.py b/litesata/frontend/common.py index 308a6c6e0..c389aa895 100644 --- a/litesata/frontend/common.py +++ b/litesata/frontend/common.py @@ -21,3 +21,7 @@ class LiteSATASlavePort: Record.connect(self.sink, master.source), Record.connect(master.sink, self.source) ] + +class LiteSATAUserPort(LiteSATASlavePort): + def __init__(self, dw): + LiteSATASlavePort.__init__(self, dw) diff --git a/litesata/frontend/crossbar.py b/litesata/frontend/crossbar.py index f4ca37aa4..d916209c0 100644 --- a/litesata/frontend/crossbar.py +++ b/litesata/frontend/crossbar.py @@ -4,7 +4,7 @@ from litesata.frontend.arbiter import LiteSATAArbiter class LiteSATACrossbar(Module): def __init__(self, core): - self.slaves = [] + self.users = [] self.master = LiteSATAMasterPort(32) self.comb += [ self.master.source.connect(core.sink), @@ -12,17 +12,15 @@ class LiteSATACrossbar(Module): ] def get_port(self): - master = LiteSATAMasterPort(32) - slave = LiteSATASlavePort(32) - self.comb += master.connect(slave) - self.slaves.append(slave) - return master + port = LiteSATAUserPort(32) + self.users += [port] + return port def get_ports(self, n): - masters = [] + ports = [] for i in range(n): - masters.append(self.get_port()) - return masters + ports.append(self.get_port()) + return ports def do_finalize(self): - self.arbiter = LiteSATAArbiter(self.slaves, self.master) + self.arbiter = LiteSATAArbiter(self.users, self.master) diff --git a/litesata/test/bist_tb.py b/litesata/test/bist_tb.py index ed8375042..e96b3c034 100644 --- a/litesata/test/bist_tb.py +++ b/litesata/test/bist_tb.py @@ -11,7 +11,7 @@ class TB(Module): link_debug=False, link_random_level=0, transport_debug=False, transport_loopback=False, hdd_debug=True) - self.controller = LiteSATA(self.hdd.phy, with_crossbar=True) + self.controller = LiteSATA(self.hdd.phy) self.generator = LiteSATABISTGenerator(self.controller.crossbar.get_port()) self.checker = LiteSATABISTChecker(self.controller.crossbar.get_port()) diff --git a/make.py b/make.py index 50e72befa..533333d9a 100644 --- a/make.py +++ b/make.py @@ -85,8 +85,7 @@ if __name__ == "__main__": revision = soc.sata_phy.revision frequency = frequencies[soc.sata_phy.revision] has_bist = hasattr(soc.sata, "bist") - has_crossbar = hasattr(soc.sata, "crossbar") - ports = 1 if not has_crossbar else len(soc.sata.crossbar.slaves) + user_ports = len(soc.sata.crossbar.users) print(""" __ _ __ _______ _________ @@ -99,14 +98,12 @@ A small footprint and configurable SATA core ====== Building options: ====== SATA revision: {} / {} MHz +User ports: {} BIST: {} -Crossbar: {} -Ports: {} ===============================""".format( revision, frequency, - has_bist, - has_crossbar, - ports + user_ports, + has_bist ) ) diff --git a/targets/bist.py b/targets/bist.py index 717ae7b19..f7ff733fb 100644 --- a/targets/bist.py +++ b/targets/bist.py @@ -141,7 +141,7 @@ class BISTSoC(GenSoC, AutoCSR): # SATA PHY/Core/Frontend self.sata_phy = LiteSATAPHY(platform.device, platform.request("sata"), "SATA2", clk_freq) self.comb += self.crg.reset.eq(self.sata_phy.ctrl.need_reset) # XXX FIXME - self.sata = LiteSATA(self.sata_phy, with_crossbar=True, with_bist=True, with_bist_csr=True) + self.sata = LiteSATA(self.sata_phy, with_bist=True, with_bist_csr=True) # Status Leds self.leds = BISTLeds(platform, self.sata_phy) diff --git a/targets/core.py b/targets/core.py index 1f0072e9e..3036a542f 100644 --- a/targets/core.py +++ b/targets/core.py @@ -17,11 +17,10 @@ class LiteSATACore(Module): # SATA PHY/Core/Frontend self.sata_phy = LiteSATAPHY(platform.device, platform.request("sata"), "SATA2", clk_freq) - self.sata = LiteSATA(self.sata_phy, with_crossbar=True) + self.sata = LiteSATA(self.sata_phy) # Get user ports from crossbar - n = 1 - self.crossbar_ports = self.sata.crossbar.get_ports(n) + self.user_ports = self.sata.crossbar.get_ports(4) def get_ios(self): # clock / reset @@ -44,12 +43,12 @@ class LiteSATACore(Module): sink_layout = command_tx_description(32).get_full_layout() source_layout = command_rx_description(32).get_full_layout() - for crossbar_port in self.crossbar_ports: + for port in self.user_ports: for e in _iter_layout(sink_layout): - obj = getattr(crossbar_port.source, e[0]) + obj = getattr(port.sink, e[0]) ios = ios.union({obj}) for e in _iter_layout(source_layout): - obj = getattr(crossbar_port.sink, e[0]) + obj = getattr(port.source, e[0]) ios = ios.union({obj}) return ios