diff --git a/misoclib/ethmac/__init__.py b/misoclib/ethmac/__init__.py
index 73b1a1712..a7ea0c2c2 100644
--- a/misoclib/ethmac/__init__.py
+++ b/misoclib/ethmac/__init__.py
@@ -10,7 +10,7 @@ from migen.bank.eventmanager import SharedIRQ
 from migen.bank.description import *
 from migen.fhdl.simplify import *
 
-from misoclib.ethmac.std import *
+from misoclib.ethmac.common import *
 from misoclib.ethmac.preamble import PreambleInserter, PreambleChecker
 from migen.actorlib.crc import CRC32Inserter, CRC32Checker
 from misoclib.ethmac.last_be import TXLastBE, RXLastBE
@@ -63,8 +63,8 @@ class EthMAC(Module, AutoCSR):
 		self.submodules.tx_pipeline = Pipeline(*tx_pipeline)
 
 		if interface == "wishbone":
-			nrxslots=2
-			ntxslots=2
+			nrxslots = 2
+			ntxslots = 2
 
 			self.bus = wishbone.Interface()
 
@@ -83,6 +83,7 @@ class EthMAC(Module, AutoCSR):
 			# Interface
 			wb_rx_sram_ifs = [wishbone.SRAM(self.sram_writer.mems[n], read_only=True)
 				for n in range(nrxslots)]
+			# TODO: FullMemoryWE should move to Mibuild
 			wb_tx_sram_ifs = [FullMemoryWE(wishbone.SRAM(self.sram_reader.mems[n], read_only=False))
 				for n in range(ntxslots)]
 			wb_sram_ifs = wb_rx_sram_ifs + wb_tx_sram_ifs
diff --git a/misoclib/ethmac/std.py b/misoclib/ethmac/common.py
similarity index 100%
rename from misoclib/ethmac/std.py
rename to misoclib/ethmac/common.py
diff --git a/misoclib/ethmac/last_be.py b/misoclib/ethmac/last_be.py
index e7fbf2ae0..80d194f0c 100644
--- a/misoclib/ethmac/last_be.py
+++ b/misoclib/ethmac/last_be.py
@@ -2,13 +2,15 @@ from migen.fhdl.std import *
 from migen.genlib.record import *
 from migen.flow.actor import Sink, Source
 
-from misoclib.ethmac.std import *
+from misoclib.ethmac.common import *
 
 class TXLastBE(Module):
 	def __init__(self, d_w):
 		self.sink = sink = Sink(eth_description(d_w))
 		self.source = source = Source(eth_description(d_w))
+
 		###
+
 		ongoing = Signal()
 		self.sync += \
 			If(self.sink.stb & self.sink.ack,
@@ -28,7 +30,10 @@ class RXLastBE(Module):
 	def __init__(self, d_w):
 		self.sink = sink = Sink(eth_description(d_w))
 		self.source = source = Source(eth_description(d_w))
+
 		###
+
+		# TODO/FIXME
 		fake = Signal() # to use RenameClockDomain
 		self.sync += fake.eq(1)
 		self.comb += [
diff --git a/misoclib/ethmac/phys/gmii.py b/misoclib/ethmac/phy/gmii.py
similarity index 94%
rename from misoclib/ethmac/phys/gmii.py
rename to misoclib/ethmac/phy/gmii.py
index f4a8210e6..ebdd02352 100644
--- a/misoclib/ethmac/phys/gmii.py
+++ b/misoclib/ethmac/phy/gmii.py
@@ -3,12 +3,14 @@ from migen.flow.actor import Sink, Source
 from migen.bank.description import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
-from misoclib.ethmac.std import *
+from misoclib.ethmac.common import *
 
 class GMIIPHYTX(Module):
 	def __init__(self, pads):
 		self.sink = sink = Sink(eth_description(8))
+
 		###
+
 		self.sync += [
 			pads.tx_er.eq(0),
 			pads.tx_en.eq(sink.stb),
@@ -19,7 +21,9 @@ class GMIIPHYTX(Module):
 class GMIIPHYRX(Module):
 	def __init__(self, pads):
 		self.source = source = Source(eth_description(8))
+
 		###
+
 		dv_d = Signal()
 		self.sync += dv_d.eq(pads.dv)
 
@@ -37,11 +41,13 @@ class GMIIPHYRX(Module):
 		self.comb += source.eop.eq(eop)
 
 # CRG is the only Xilinx specific module.
-# Todo: use generic code or add support for others vendors
+# TODO: use generic code or add support for others vendors
 class GMIIPHYCRG(Module, AutoCSR):
 	def __init__(self, clock_pads, pads):
 		self._reset = CSRStorage()
+
 		###
+
 		self.clock_domains.cd_eth_rx = ClockDomain()
 		self.clock_domains.cd_eth_tx = ClockDomain()
 		self.specials += [
@@ -64,7 +70,6 @@ class GMIIPHYCRG(Module, AutoCSR):
 class GMIIPHY(Module, AutoCSR):
 	def __init__(self, clock_pads, pads):
 		self.dw = 8
-		###
 		self.submodules.crg = GMIIPHYCRG(clock_pads, pads)
 		self.submodules.tx = RenameClockDomains(GMIIPHYTX(pads), "eth_tx")
 		self.submodules.rx = RenameClockDomains(GMIIPHYRX(pads), "eth_rx")
diff --git a/misoclib/ethmac/phys/loopback.py b/misoclib/ethmac/phy/loopback.py
similarity index 95%
rename from misoclib/ethmac/phys/loopback.py
rename to misoclib/ethmac/phy/loopback.py
index 9e8d83c38..50c9f995d 100644
--- a/misoclib/ethmac/phys/loopback.py
+++ b/misoclib/ethmac/phy/loopback.py
@@ -3,12 +3,14 @@ from migen.flow.actor import Sink, Source
 from migen.bank.description import *
 from migen.genlib.record import *
 
-from misoclib.ethmac.std import *
+from misoclib.ethmac.common import *
 
 class LoopbackPHYCRG(Module, AutoCSR):
 	def __init__(self):
 		self._reset = CSRStorage()
+
 		###
+
 		self.clock_domains.cd_eth_rx = ClockDomain()
 		self.clock_domains.cd_eth_tx = ClockDomain()
 		self.comb += [
@@ -25,7 +27,6 @@ class LoopbackPHYCRG(Module, AutoCSR):
 class LoopbackPHY(Module, AutoCSR):
 	def __init__(self):
 		self.dw = 8
-		###
 		self.submodules.crg = LoopbackPHYCRG()
 		self.sink = sink = Sink(eth_description(8))
 		self.source = source = Source(eth_description(8))
diff --git a/misoclib/ethmac/phys/mii.py b/misoclib/ethmac/phy/mii.py
similarity index 98%
rename from misoclib/ethmac/phys/mii.py
rename to misoclib/ethmac/phy/mii.py
index 5dba08cff..17f2ba7b4 100644
--- a/misoclib/ethmac/phys/mii.py
+++ b/misoclib/ethmac/phy/mii.py
@@ -4,12 +4,14 @@ from migen.flow.actor import Sink, Source
 from migen.bank.description import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
-from misoclib.ethmac.std import *
+from misoclib.ethmac.common import *
 
 class MIIPHYTX(Module):
 	def __init__(self, pads):
 		self.sink = sink = Sink(eth_description(8))
+
 		###
+
 		tx_en_r = Signal()
 		tx_data_r = Signal(4)
 		self.sync += [
@@ -46,7 +48,9 @@ class MIIPHYTX(Module):
 class MIIPHYRX(Module):
 	def __init__(self, pads):
 		self.source = source = Source(eth_description(8))
+
 		###
+
 		sop = source.sop
 		set_sop = Signal()
 		clr_sop = Signal()
@@ -98,7 +102,9 @@ class MIIPHYRX(Module):
 class MIIPHYCRG(Module, AutoCSR):
 	def __init__(self, clock_pads, pads):
 		self._reset = CSRStorage()
+
 		###
+
 		self.sync.base50 += clock_pads.phy.eq(~clock_pads.phy)
 
 		self.clock_domains.cd_eth_rx = ClockDomain()
@@ -116,7 +122,6 @@ class MIIPHYCRG(Module, AutoCSR):
 class MIIPHY(Module, AutoCSR):
 	def __init__(self, clock_pads, pads):
 		self.dw = 8
-		###
 		self.submodules.crg = MIIPHYCRG(clock_pads, pads)
 		self.submodules.tx = RenameClockDomains(MIIPHYTX(pads), "eth_tx")
 		self.submodules.rx = RenameClockDomains(MIIPHYRX(pads), "eth_rx")
diff --git a/misoclib/ethmac/preamble.py b/misoclib/ethmac/preamble.py
index db693b4ae..fe2078fee 100644
--- a/misoclib/ethmac/preamble.py
+++ b/misoclib/ethmac/preamble.py
@@ -4,7 +4,7 @@ from migen.genlib.misc import chooser
 from migen.genlib.record import *
 from migen.flow.actor import Sink, Source
 
-from misoclib.ethmac.std import *
+from misoclib.ethmac.common import *
 
 class PreambleInserter(Module):
 	def __init__(self, d_w):
@@ -63,7 +63,7 @@ class PreambleChecker(Module):
 		###
 
 		preamble = Signal(64, reset=eth_preamble)
-		cnt_max = (64//d_w)-1
+		cnt_max = (64//d_w) - 1
 		cnt = Signal(max=cnt_max+1)
 		clr_cnt = Signal()
 		inc_cnt = Signal()
diff --git a/misoclib/ethmac/sram.py b/misoclib/ethmac/sram.py
index 5160a8f6f..32c76f3c0 100644
--- a/misoclib/ethmac/sram.py
+++ b/misoclib/ethmac/sram.py
@@ -6,7 +6,7 @@ from migen.flow.actor import Sink, Source
 from migen.bank.description import *
 from migen.bank.eventmanager import *
 
-from misoclib.ethmac.std import *
+from misoclib.ethmac.common import *
 
 class SRAMWriter(Module, AutoCSR):
 	def __init__(self, depth, nslots=2):
@@ -25,10 +25,10 @@ class SRAMWriter(Module, AutoCSR):
 
 		###
 
-	# packet dropped if no slot available
+		# packet dropped if no slot available
 		sink.ack.reset = 1
 
-	# length computation
+		# length computation
 		cnt = Signal(lengthbits)
 		clr_cnt = Signal()
 		inc_cnt = Signal()
@@ -50,7 +50,7 @@ class SRAMWriter(Module, AutoCSR):
 				cnt.eq(cnt+inc_val)
 			)
 
-	# slot computation
+		# slot computation
 		slot = Signal(slotbits)
 		inc_slot = Signal()
 		self.sync += \
@@ -64,11 +64,11 @@ class SRAMWriter(Module, AutoCSR):
 		ongoing = Signal()
 		discard = Signal()
 
-	# status fifo
+		# status fifo
 		fifo = SyncFIFO([("slot", slotbits), ("length", lengthbits)], nslots)
 		self.submodules += fifo
 
-	# fsm
+		# fsm
 		fsm = FSM(reset_state="IDLE")
 		self.submodules += fsm
 
@@ -112,7 +112,7 @@ class SRAMWriter(Module, AutoCSR):
 			self._length.status.eq(fifo.dout.length),
 		]
 
-	# memory
+		# memory
 		mems = [None]*nslots
 		ports = [None]*nslots
 		for n in range(nslots):
@@ -152,7 +152,7 @@ class SRAMReader(Module, AutoCSR):
 
 		###
 
-	# command fifo
+		# command fifo
 		fifo = SyncFIFO([("slot", slotbits), ("length", lengthbits)], nslots)
 		self.submodules += fifo
 		self.comb += [
@@ -162,7 +162,7 @@ class SRAMReader(Module, AutoCSR):
 			self._ready.status.eq(fifo.writable)
 		]
 
-	# length computation
+		# length computation
 		cnt = Signal(lengthbits)
 		clr_cnt = Signal()
 		inc_cnt = Signal()
@@ -174,7 +174,7 @@ class SRAMReader(Module, AutoCSR):
 				cnt.eq(cnt+4)
 			)
 
-	# fsm
+		# fsm
 		first = Signal()
 		last  = Signal()
 		last_d = Signal()
@@ -222,7 +222,7 @@ class SRAMReader(Module, AutoCSR):
 			NextState("IDLE")
 		)
 
-	# first/last computation
+		# first/last computation
 		self.sync += [
 			If(fsm.ongoing("IDLE"),
 				first.eq(1)
@@ -230,10 +230,10 @@ class SRAMReader(Module, AutoCSR):
 				first.eq(0)
 			)
 		]
-		self.comb += last.eq(cnt+4 >= fifo.dout.length)
+		self.comb += last.eq(cnt + 4 >= fifo.dout.length)
 		self.sync += last_d.eq(last)
 
-	# memory
+		# memory
 		rd_slot = fifo.dout.slot
 
 		mems = [None]*nslots
diff --git a/misoclib/ethmac/test/Makefile b/misoclib/ethmac/test/Makefile
deleted file mode 100644
index 55d28e10a..000000000
--- a/misoclib/ethmac/test/Makefile
+++ /dev/null
@@ -1,13 +0,0 @@
-MSCDIR = ../../../
-PYTHON = python3
-
-CMD = PYTHONPATH=$(MSCDIR) $(PYTHON)
-
-crc_tb:
-	$(CMD) crc_tb.py
-
-preamble_tb:
-	$(CMD) preamble_tb.py
-
-ethmac_tb:
-	$(CMD) ethmac_tb.py
diff --git a/misoclib/ethmac/test/__init__.py b/misoclib/ethmac/test/__init__.py
index f3ad9525f..d5dcc35c9 100644
--- a/misoclib/ethmac/test/__init__.py
+++ b/misoclib/ethmac/test/__init__.py
@@ -1,8 +1,9 @@
 import random
+
 from migen.fhdl.std import *
 from migen.flow.actor import Sink, Source
 
-from misoclib.ethmac.std import *
+from misoclib.ethmac.common import *
 
 class PacketStreamer(Module):
 	def __init__(self, data):
@@ -16,10 +17,10 @@ class PacketStreamer(Module):
 			selfp.source.eop = (n == len(self.data)-1)
 			selfp.source.payload.d = data
 			yield
-			while (selfp.source.ack == 0):
+			while selfp.source.ack == 0:
 				yield
 			selfp.source.stb = 0
-			while (bool(random.getrandbits(1)) == 0):
+			while random.getrandbits(1):
 				yield
 
 class PacketLogger(Module):
@@ -29,7 +30,7 @@ class PacketLogger(Module):
 
 	def do_simulation(self, selfp):
 		selfp.sink.ack = bool(random.getrandbits(1))
-		if selfp.sink.stb == 1 and selfp.sink.ack:
+		if selfp.sink.stb and selfp.sink.ack:
 			self.data.append(selfp.sink.payload.d)
 
 def print_results(s, l1, l2):
@@ -38,7 +39,7 @@ def print_results(s, l1, l2):
 		try:
 			for i, val in enumerate(l1):
 				if val != l2[i]:
-					print(s + " : val : %02X, exp : %02X" %(val, l2[i]))
+					print(s + " : val : {:02X}, exp : {:02X}".format(val, l2[i]))
 					r = False
 		except:
 			r = False
diff --git a/misoclib/ethmac/test/crc_tb.py b/misoclib/ethmac/test/crc_tb.py
index 74fab2840..8c5816e1d 100644
--- a/misoclib/ethmac/test/crc_tb.py
+++ b/misoclib/ethmac/test/crc_tb.py
@@ -1,8 +1,7 @@
 from migen.fhdl.std import *
 from migen.actorlib.crc import *
 
-from misoclib.ethmac.std import *
-
+from misoclib.ethmac.common import *
 from misoclib.ethmac.test import *
 
 frame_data = [
@@ -22,10 +21,9 @@ frame_crc = [
 
 class TB(Module):
 	def __init__(self):
-
 		sm = self.submodules
 
-	# Streamer (DATA) --> CRC32Inserter --> Logger (expect DATA + CRC)
+		# Streamer (DATA) --> CRC32Inserter --> Logger (expect DATA + CRC)
 		sm.inserter_streamer = PacketStreamer(frame_data)
 		sm.crc32_inserter = CRC32Inserter(eth_description(8))
 		sm.inserter_logger = PacketLogger()
@@ -34,8 +32,8 @@ class TB(Module):
 			self.crc32_inserter.source.connect(self.inserter_logger.sink),
 		]
 
-	# Streamer (DATA + CRC) --> CRC32Checher --> Logger (except DATA + CRC + check)
-		sm.checker_streamer = PacketStreamer(frame_data+frame_crc)
+		# Streamer (DATA + CRC) --> CRC32Checher --> Logger (except DATA + CRC + check)
+		sm.checker_streamer = PacketStreamer(frame_data + frame_crc)
 		sm.crc32_checker = CRC32Checker(eth_description(8))
 		sm.checker_logger = PacketLogger()
 		self.comb +=[
@@ -55,7 +53,6 @@ class TB(Module):
 		print_results("inserter", inserter_reference, inserter_generated)
 		print_results("checker", checker_reference, checker_generated)
 
-
 if __name__ == "__main__":
 	from migen.sim.generic import run_simulation
 	run_simulation(TB(), ncycles=1000, vcd_name="my.vcd", keep_files=True)
diff --git a/misoclib/ethmac/test/ethmac_tb.py b/misoclib/ethmac/test/ethmac_tb.py
index 7a02f35cd..3086ceb0e 100644
--- a/misoclib/ethmac/test/ethmac_tb.py
+++ b/misoclib/ethmac/test/ethmac_tb.py
@@ -4,9 +4,9 @@ from migen.bus.transactions import *
 from migen.sim.generic import run_simulation
 
 from misoclib.ethmac import EthMAC
-from misoclib.ethmac.phys import loopback
+from misoclib.ethmac.phy import loopback
 
-class WishboneMaster():
+class WishboneMaster:
 	def __init__(self, obj):
 		self.obj = obj
 		self.dat = 0
@@ -38,7 +38,7 @@ class WishboneMaster():
 		self.obj.stb = 0
 		yield
 
-class SRAMReaderDriver():
+class SRAMReaderDriver:
 	def __init__(self, obj):
 		self.obj = obj
 
@@ -53,6 +53,7 @@ class SRAMReaderDriver():
 	def wait_done(self):
 		while self.obj.ev.done.pending == 0:
 			yield
+
 	def clear_done(self):
 		self.obj.ev.done.clear = 1
 		yield
@@ -89,7 +90,7 @@ class TB(Module):
 
 		length = 1500-2
 
-		payload = [i%0xFF for i in range(length)] + [0, 0, 0, 0]
+		payload = [i % 0xFF for i in range(length)] + [0, 0, 0, 0]
 
 		errors = 0
 
@@ -120,7 +121,7 @@ class TB(Module):
 
 			# check rx data
 			for i in range(length):
-				#print("%02x / %02x" %(rx_dat[i], payload[i]))
+				#print("{:02x} / {:02x}".format(rx_dat[i], payload[i]))
 				if rx_dat[i] != payload[i]:
 					errors += 1
 
@@ -128,7 +129,7 @@ class TB(Module):
 			yield
 		#print(selfp.ethmac.sram_reader._length.storage)
 
-		print("Errors : %d" %errors)
+		print("Errors : {}".format(errors))
 
 if __name__ == "__main__":
 	run_simulation(TB(), ncycles=16000, vcd_name="my.vcd", keep_files=True)
diff --git a/misoclib/ethmac/test/preamble_tb.py b/misoclib/ethmac/test/preamble_tb.py
index 8fca916dd..6505e043f 100644
--- a/misoclib/ethmac/test/preamble_tb.py
+++ b/misoclib/ethmac/test/preamble_tb.py
@@ -1,8 +1,7 @@
 from migen.fhdl.std import *
 
-from misoclib.ethmac.std import *
+from misoclib.ethmac.common import *
 from misoclib.ethmac.preamble import *
-
 from misoclib.ethmac.test import *
 
 frame_preamble = [
@@ -22,10 +21,9 @@ frame_data = [
 
 class TB(Module):
 	def __init__(self):
-
 		sm = self.submodules
 
-	# Streamer (DATA) --> PreambleInserter --> Logger (expect PREAMBLE + DATA)
+		# Streamer (DATA) --> PreambleInserter --> Logger (expect PREAMBLE + DATA)
 		sm.inserter_streamer = PacketStreamer(frame_data)
 		sm.preamble_inserter = PreambleInserter(8)
 		sm.inserter_logger = PacketLogger()
@@ -34,7 +32,7 @@ class TB(Module):
 			self.preamble_inserter.source.connect(self.inserter_logger.sink),
 		]
 
-	# Streamer (PREAMBLE + DATA) --> CRC32Checher --> Logger (except DATA + check)
+		# Streamer (PREAMBLE + DATA) --> CRC32Checher --> Logger (except DATA + check)
 		sm.checker_streamer = PacketStreamer(frame_preamble + frame_data)		
 		sm.preamble_checker = PreambleChecker(8)
 		sm.checker_logger = PacketLogger()
@@ -43,7 +41,6 @@ class TB(Module):
 			self.preamble_checker.source.connect(self.checker_logger.sink),
 		]
 
-
 	def gen_simulation(self, selfp):
 		for i in range(500):
 			yield
diff --git a/targets/kc705.py b/targets/kc705.py
index 5680a0e7a..cd0df7696 100644
--- a/targets/kc705.py
+++ b/targets/kc705.py
@@ -4,7 +4,7 @@ from migen.genlib.resetsync import AsyncResetSynchronizer
 from misoclib import lasmicon, spiflash, ethmac
 from misoclib.sdramphy import k7ddrphy
 from misoclib.gensoc import SDRAMSoC
-from misoclib.ethmac.phys import gmii
+from misoclib.ethmac.phy import gmii
 
 class _CRG(Module):
 	def __init__(self, platform):
diff --git a/targets/mlabs_video.py b/targets/mlabs_video.py
index d23380158..869f232cd 100644
--- a/targets/mlabs_video.py
+++ b/targets/mlabs_video.py
@@ -7,7 +7,7 @@ from mibuild.generic_platform import ConstraintError
 from misoclib import lasmicon, mxcrg, norflash16, ethmac, framebuffer, gpio
 from misoclib.sdramphy import s6ddrphy
 from misoclib.gensoc import SDRAMSoC
-from misoclib.ethmac.phys import mii
+from misoclib.ethmac.phy import mii
 
 class _MXClockPads:
 	def __init__(self, platform):