From 336728413ae4e93c05633592cc7e002952d1765b Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Sat, 12 Sep 2015 19:34:07 +0800
Subject: [PATCH] simplify imports, migen.fhdl.std -> migen

---
 README.md                       |  2 +-
 doc/fhdl.rst                    |  2 +-
 examples/basic/arrays.py        |  5 +++--
 examples/basic/fsm.py           |  9 ++++-----
 examples/basic/graycounter.py   |  3 +--
 examples/basic/instance.py      |  3 +--
 examples/basic/local_cd.py      |  7 ++++---
 examples/basic/memory.py        |  8 +++++---
 examples/basic/namer.py         |  2 +-
 examples/basic/psync.py         | 10 ++++++----
 examples/basic/record.py        | 12 +++++++-----
 examples/basic/reslice.py       |  6 ++++--
 examples/basic/tristate.py      |  7 ++++---
 examples/basic/two_dividers.py  |  7 ++++---
 examples/sim/basic1.py          |  3 +--
 examples/sim/basic2.py          |  3 +--
 examples/sim/fir.py             |  8 ++++----
 examples/sim/memory.py          |  3 +--
 migen/__init__.py               | 10 ++++++++++
 migen/build/altera/common.py    |  3 ++-
 migen/build/generic_platform.py |  3 +--
 migen/build/lattice/common.py   |  8 ++++----
 migen/build/sim/verilator.py    |  8 ++------
 migen/build/xilinx/common.py    |  4 +++-
 migen/build/xilinx/ise.py       |  1 -
 migen/build/xilinx/vivado.py    |  2 --
 migen/fhdl/bitcontainer.py      |  3 +++
 migen/fhdl/decorators.py        |  6 ++++++
 migen/fhdl/edif.py              |  5 ++---
 migen/fhdl/module.py            |  3 +++
 migen/fhdl/simplify.py          |  2 +-
 migen/fhdl/specials.py          |  7 ++++++-
 migen/fhdl/std.py               |  7 -------
 migen/genlib/cdc.py             |  6 +++---
 migen/genlib/coding.py          |  5 +++--
 migen/genlib/divider.py         |  3 ++-
 migen/genlib/fifo.py            |  4 +++-
 migen/genlib/fsm.py             |  7 +++++--
 migen/genlib/io.py              |  4 ++--
 migen/genlib/misc.py            |  3 ++-
 migen/genlib/record.py          |  2 +-
 migen/genlib/resetsync.py       |  3 +--
 migen/genlib/roundrobin.py      |  4 +++-
 migen/genlib/sort.py            |  3 ++-
 migen/sim.py                    |  5 ++++-
 migen/test/support.py           |  3 +--
 migen/test/test_coding.py       |  2 +-
 migen/test/test_fifo.py         |  2 +-
 migen/test/test_signed.py       |  2 +-
 migen/test/test_size.py         |  2 +-
 migen/test/test_sort.py         |  2 +-
 migen/test/test_syntax.py       |  2 +-
 52 files changed, 134 insertions(+), 102 deletions(-)
 delete mode 100644 migen/fhdl/std.py

diff --git a/README.md b/README.md
index e90a59f34..39f8e96a5 100644
--- a/README.md
+++ b/README.md
@@ -47,7 +47,7 @@ http://m-labs.hk/gateware.html
 #### Quick intro
 
 ```python
-from migen.fhdl.std import *
+from migen import *
 from migen.build.platforms import m1
 plat = m1.Platform()
 led = plat.request("user_led")
diff --git a/doc/fhdl.rst b/doc/fhdl.rst
index 9eec89dfe..85e78842c 100644
--- a/doc/fhdl.rst
+++ b/doc/fhdl.rst
@@ -8,7 +8,7 @@ FHDL differs from MyHDL [myhdl]_ in fundamental ways. MyHDL follows the event-dr
 
 .. [myhdl] http://www.myhdl.org
 
-FHDL is made of several elements, which are briefly explained below. They all can be imported from the ``migen.fhdl.std`` module.
+FHDL is made of several elements, which are briefly explained below. They all can be imported directly from the ``migen`` module.
 
 Expressions
 ***********
diff --git a/examples/basic/arrays.py b/examples/basic/arrays.py
index 5141d8ecd..0753107cb 100644
--- a/examples/basic/arrays.py
+++ b/examples/basic/arrays.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.fhdl import verilog
 
 
@@ -24,4 +24,5 @@ class Example(Module):
         outa = Array(Signal() for a in range(dy))
         self.specials += Instance("test", o_O=outa[y], i_I=ina[x])
 
-print(verilog.convert(Example()))
+if __name__ == "__main__":
+    print(verilog.convert(Example()))
diff --git a/examples/basic/fsm.py b/examples/basic/fsm.py
index 4c2c87926..dff6f4d53 100644
--- a/examples/basic/fsm.py
+++ b/examples/basic/fsm.py
@@ -1,7 +1,5 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.fhdl import verilog
-from migen.genlib.fsm import FSM, NextState, NextValue
-
 
 class Example(Module):
     def __init__(self):
@@ -26,5 +24,6 @@ class Example(Module):
         self.bl = myfsm.before_leaving("FOO")
         self.al = myfsm.after_leaving("FOO")
 
-example = Example()
-print(verilog.convert(example, {example.s, example.counter, example.be, example.ae, example.bl, example.al}))
+if __name__ == "__main__":
+    example = Example()
+    print(verilog.convert(example, {example.s, example.counter, example.be, example.ae, example.bl, example.al}))
diff --git a/examples/basic/graycounter.py b/examples/basic/graycounter.py
index d36163504..bedd46658 100644
--- a/examples/basic/graycounter.py
+++ b/examples/basic/graycounter.py
@@ -1,8 +1,7 @@
 from random import Random
 
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.cdc import GrayCounter
-from migen.sim import Simulator
 
 
 def tb(dut):
diff --git a/examples/basic/instance.py b/examples/basic/instance.py
index e29420e8a..fcabecc14 100644
--- a/examples/basic/instance.py
+++ b/examples/basic/instance.py
@@ -1,7 +1,6 @@
 import subprocess
 
-from migen.fhdl.std import *
-from migen.fhdl.specials import Instance
+from migen import *
 from migen.fhdl.verilog import convert
 
 
diff --git a/examples/basic/local_cd.py b/examples/basic/local_cd.py
index 3fddcec58..dc0550601 100644
--- a/examples/basic/local_cd.py
+++ b/examples/basic/local_cd.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.fhdl import verilog
 from migen.genlib.divider import Divider
 
@@ -14,5 +14,6 @@ class MultiMod(Module):
         self.submodules.foo = CDM()
         self.submodules.bar = CDM()
 
-mm = MultiMod()
-print(verilog.convert(mm, {mm.foo.cd_sys.clk, mm.bar.cd_sys.clk}))
+if __name__ == "__main__":
+    mm = MultiMod()
+    print(verilog.convert(mm, {mm.foo.cd_sys.clk, mm.bar.cd_sys.clk}))
diff --git a/examples/basic/memory.py b/examples/basic/memory.py
index e20b4a9f8..6b9c1f2c7 100644
--- a/examples/basic/memory.py
+++ b/examples/basic/memory.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.fhdl import verilog
 
 
@@ -11,5 +11,7 @@ class Example(Module):
         self.ios = {p1.adr, p1.dat_r, p1.we, p1.dat_w,
             p2.adr, p2.dat_r, p2.re}
 
-example = Example()
-print(verilog.convert(example, example.ios))
+
+if __name__ == "__main__":
+    example = Example()
+    print(verilog.convert(example, example.ios))
diff --git a/examples/basic/namer.py b/examples/basic/namer.py
index 670de37e2..0c30c8147 100644
--- a/examples/basic/namer.py
+++ b/examples/basic/namer.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.fhdl import verilog
 
 from functools import reduce
diff --git a/examples/basic/psync.py b/examples/basic/psync.py
index 64f704f82..034ca69fc 100644
--- a/examples/basic/psync.py
+++ b/examples/basic/psync.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.fhdl.specials import SynthesisDirective
 from migen.fhdl import verilog
 from migen.genlib.cdc import *
@@ -16,6 +16,8 @@ class XilinxMultiReg:
     def lower(dr):
         return XilinxMultiRegImpl(dr.i, dr.o, dr.odomain, dr.n)
 
-ps = PulseSynchronizer("from", "to")
-v = verilog.convert(ps, {ps.i, ps.o}, special_overrides={MultiReg: XilinxMultiReg})
-print(v)
+
+if __name__ == "__main__":
+    ps = PulseSynchronizer("from", "to")
+    v = verilog.convert(ps, {ps.i, ps.o}, special_overrides={MultiReg: XilinxMultiReg})
+    print(v)
diff --git a/examples/basic/record.py b/examples/basic/record.py
index 7b31a18c0..59e72774b 100644
--- a/examples/basic/record.py
+++ b/examples/basic/record.py
@@ -1,6 +1,6 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.fhdl import verilog
-from migen.genlib.record import *
+
 
 L = [
     ("position", [
@@ -19,6 +19,8 @@ class Test(Module):
         slave = Record(L)
         self.comb += master.connect(slave)
 
-print(verilog.convert(Test()))
-print(layout_len(L))
-print(layout_partial(L, "position/x", "color"))
+
+if __name__ == "__main__":
+    print(verilog.convert(Test()))
+    print(layout_len(L))
+    print(layout_partial(L, "position/x", "color"))
diff --git a/examples/basic/reslice.py b/examples/basic/reslice.py
index a86f75af0..c5fb502a5 100644
--- a/examples/basic/reslice.py
+++ b/examples/basic/reslice.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.fhdl import verilog
 
 
@@ -14,4 +14,6 @@ class Example(Module):
         self.comb += s3.eq(0)
         self.comb += d.eq(Cat(d[::-1], Cat(s1[:1], s3[-4:])[:3]))
 
-print(verilog.convert(Example()))
+
+if __name__ == "__main__":
+    print(verilog.convert(Example()))
diff --git a/examples/basic/tristate.py b/examples/basic/tristate.py
index 9359aaa06..51afa033d 100644
--- a/examples/basic/tristate.py
+++ b/examples/basic/tristate.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.fhdl import verilog
 
 
@@ -8,5 +8,6 @@ class Example(Module):
         self.t = TSTriple(n)
         self.specials += self.t.get_tristate(self.pad)
 
-e = Example()
-print(verilog.convert(e, ios={e.pad, e.t.o, e.t.oe, e.t.i}))
+if __name__ == "__main__":
+    e = Example()
+    print(verilog.convert(e, ios={e.pad, e.t.o, e.t.oe, e.t.i}))
diff --git a/examples/basic/two_dividers.py b/examples/basic/two_dividers.py
index 5e70cfbe3..6869d548e 100644
--- a/examples/basic/two_dividers.py
+++ b/examples/basic/two_dividers.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.fhdl import verilog
 from migen.genlib import divider
 
@@ -14,5 +14,6 @@ class Example(Module):
             d1.ready_o, d1.quotient_o, d1.remainder_o, d1.start_i, d1.dividend_i, d1.divisor_i,
             d2.ready_o, d2.quotient_o, d2.remainder_o, d2.start_i, d2.dividend_i, d2.divisor_i}
 
-example = Example(16)
-print(verilog.convert(example, example.ios | {example.ce, example.reset}))
+if __name__ == "__main__":
+    example = Example(16)
+    print(verilog.convert(example, example.ios | {example.ce, example.reset}))
diff --git a/examples/sim/basic1.py b/examples/sim/basic1.py
index 9da2f460b..e9426fce5 100644
--- a/examples/sim/basic1.py
+++ b/examples/sim/basic1.py
@@ -1,5 +1,4 @@
-from migen.fhdl.std import *
-from migen.sim import Simulator
+from migen import *
 
 
 # Our simple counter, which increments at every cycle.
diff --git a/examples/sim/basic2.py b/examples/sim/basic2.py
index 2b6eabe5c..524f4435b 100644
--- a/examples/sim/basic2.py
+++ b/examples/sim/basic2.py
@@ -1,5 +1,4 @@
-from migen.fhdl.std import *
-from migen.sim import Simulator
+from migen import *
 
 
 # A slightly more elaborate counter.
diff --git a/examples/sim/fir.py b/examples/sim/fir.py
index ffc6b78a7..c9adcb2cd 100644
--- a/examples/sim/fir.py
+++ b/examples/sim/fir.py
@@ -1,13 +1,13 @@
+from functools import reduce
+from operator import add
+
 from math import cos, pi
 from scipy import signal
 import matplotlib.pyplot as plt
 
-from migen.fhdl.std import *
+from migen import *
 from migen.fhdl import verilog
-from migen.sim import Simulator
 
-from functools import reduce
-from operator import add
 
 # A synthesizable FIR filter.
 class FIR(Module):
diff --git a/examples/sim/memory.py b/examples/sim/memory.py
index db9bde571..7bd3d5fb0 100644
--- a/examples/sim/memory.py
+++ b/examples/sim/memory.py
@@ -1,5 +1,4 @@
-from migen.fhdl.std import *
-from migen.sim.generic import run_simulation
+from migen import *
 
 
 class Mem(Module):
diff --git a/migen/__init__.py b/migen/__init__.py
index e69de29bb..492117f22 100644
--- a/migen/__init__.py
+++ b/migen/__init__.py
@@ -0,0 +1,10 @@
+from migen.fhdl.structure import *
+from migen.fhdl.module import *
+from migen.fhdl.specials import *
+from migen.fhdl.bitcontainer import *
+from migen.fhdl.decorators import *
+
+from migen.sim import *
+
+from migen.genlib.record import *
+from migen.genlib.fsm import *
diff --git a/migen/build/altera/common.py b/migen/build/altera/common.py
index 56e206557..554461da7 100644
--- a/migen/build/altera/common.py
+++ b/migen/build/altera/common.py
@@ -1,4 +1,5 @@
-from migen.fhdl.std import Instance, Module
+from migen.fhdl.module import Module
+from migen.fhdl.specials import Instance
 from migen.genlib.io import DifferentialInput, DifferentialOutput
 
 
diff --git a/migen/build/generic_platform.py b/migen/build/generic_platform.py
index ff8a51e34..e6537184c 100644
--- a/migen/build/generic_platform.py
+++ b/migen/build/generic_platform.py
@@ -1,12 +1,11 @@
 import os
 import sys
 
-from migen.fhdl.std import Signal
+from migen.fhdl.structure import Signal
 from migen.genlib.record import Record
 from migen.genlib.io import CRG
 from migen.fhdl import verilog, edif
 from migen.util.misc import autotype
-
 from migen.build import tools
 
 
diff --git a/migen/build/lattice/common.py b/migen/build/lattice/common.py
index 090d3fc0b..c25e8b903 100644
--- a/migen/build/lattice/common.py
+++ b/migen/build/lattice/common.py
@@ -1,6 +1,6 @@
-from migen.fhdl.std import *
+from migen.fhdl.module import Module
+from migen.fhdl.specials import Instance
 from migen.genlib.io import *
-
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
 
@@ -36,6 +36,6 @@ class LatticeDDROutput:
         return LatticeDDROutputImpl(dr.i1, dr.i2, dr.o, dr.clk)
 
 lattice_special_overrides = {
-    AsyncResetSynchronizer:    LatticeAsyncResetSynchronizer,
-    DDROutput:    LatticeDDROutput
+    AsyncResetSynchronizer: LatticeAsyncResetSynchronizer,
+    DDROutput: LatticeDDROutput
 }
diff --git a/migen/build/sim/verilator.py b/migen/build/sim/verilator.py
index fd1d8be9d..4e6355288 100644
--- a/migen/build/sim/verilator.py
+++ b/migen/build/sim/verilator.py
@@ -4,18 +4,14 @@
 import os
 import subprocess
 
-from migen.fhdl.std import *
 from migen.fhdl.structure import _Fragment
-
 from migen.build import tools
 from migen.build.generic_platform import *
-from migen.build.sim import common
 
 
 def _build_tb(platform, vns, serial, template):
-
-    def io_name(ressource, subsignal=None):
-        res = platform.lookup_request(ressource)
+    def io_name(resource, subsignal=None):
+        res = platform.lookup_request(resource)
         if subsignal is not None:
             res = getattr(res, subsignal)
         return vns.get_name(res)
diff --git a/migen/build/xilinx/common.py b/migen/build/xilinx/common.py
index 7c753ab69..52f8ca970 100644
--- a/migen/build/xilinx/common.py
+++ b/migen/build/xilinx/common.py
@@ -2,7 +2,9 @@ import os
 import sys
 from distutils.version import StrictVersion
 
-from migen.fhdl.std import *
+from migen.fhdl.structure import *
+from migen.fhdl.specials import Instance
+from migen.fhdl.module import Module
 from migen.fhdl.specials import SynthesisDirective
 from migen.genlib.cdc import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
diff --git a/migen/build/xilinx/ise.py b/migen/build/xilinx/ise.py
index 65126a108..0d0709cda 100644
--- a/migen/build/xilinx/ise.py
+++ b/migen/build/xilinx/ise.py
@@ -2,7 +2,6 @@ import os
 import subprocess
 import sys
 
-from migen.fhdl.std import *
 from migen.fhdl.structure import _Fragment
 from migen.build.generic_platform import *
 from migen.build import tools
diff --git a/migen/build/xilinx/vivado.py b/migen/build/xilinx/vivado.py
index 8d85885f4..da2bd7105 100644
--- a/migen/build/xilinx/vivado.py
+++ b/migen/build/xilinx/vivado.py
@@ -5,9 +5,7 @@ import os
 import subprocess
 import sys
 
-from migen.fhdl.std import *
 from migen.fhdl.structure import _Fragment
-
 from migen.build.generic_platform import *
 from migen.build import tools
 from migen.build.xilinx import common
diff --git a/migen/fhdl/bitcontainer.py b/migen/fhdl/bitcontainer.py
index 9763845f1..7eded12f9 100644
--- a/migen/fhdl/bitcontainer.py
+++ b/migen/fhdl/bitcontainer.py
@@ -1,6 +1,9 @@
 from migen.fhdl import structure as f
 
 
+__all__ = ["log2_int", "bits_for", "flen", "fiter", "fslice", "freversed"]
+
+
 def log2_int(n, need_pow2=True):
     l = 1
     r = 0
diff --git a/migen/fhdl/decorators.py b/migen/fhdl/decorators.py
index 7a1f82115..00ea2d224 100644
--- a/migen/fhdl/decorators.py
+++ b/migen/fhdl/decorators.py
@@ -5,6 +5,12 @@ from migen.fhdl.module import Module
 from migen.fhdl.tools import insert_reset, rename_clock_domain
 
 
+__all__ = ["DecorateModule",
+           "InsertCE", "InsertReset", "RenameClockDomains",
+           "CEInserter", "ResetInserter", "ClockDomainsRenamer",
+           "ModuleTransformer"]
+
+
 class ModuleTransformer:
     # overload this in derived classes
     def transform_instance(self, i):
diff --git a/migen/fhdl/edif.py b/migen/fhdl/edif.py
index 32c3cf9f5..f6d7deb0e 100644
--- a/migen/fhdl/edif.py
+++ b/migen/fhdl/edif.py
@@ -1,7 +1,6 @@
-from collections import OrderedDict
-from collections import namedtuple
+from collections import OrderedDict, namedtuple
 
-from migen.fhdl.std import *
+from migen.fhdl.structure import *
 from migen.fhdl.namer import build_namespace
 from migen.fhdl.tools import list_special_ios
 from migen.fhdl.structure import _Fragment
diff --git a/migen/fhdl/module.py b/migen/fhdl/module.py
index 3c9d558a8..7a2099335 100644
--- a/migen/fhdl/module.py
+++ b/migen/fhdl/module.py
@@ -7,6 +7,9 @@ from migen.fhdl.structure import _Fragment
 from migen.fhdl.tools import rename_clock_domain
 
 
+__all__ = ["Module", "FinalizeError"]
+
+
 class FinalizeError(Exception):
     pass
 
diff --git a/migen/fhdl/simplify.py b/migen/fhdl/simplify.py
index 66e4e58bf..b1afb0d5a 100644
--- a/migen/fhdl/simplify.py
+++ b/migen/fhdl/simplify.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen.fhdl.structure import *
 from migen.fhdl.specials import _MemoryPort
 from migen.fhdl.decorators import ModuleTransformer
 from migen.util.misc import gcd_multiple
diff --git a/migen/fhdl/specials.py b/migen/fhdl/specials.py
index cb176a8bc..e488bb47c 100644
--- a/migen/fhdl/specials.py
+++ b/migen/fhdl/specials.py
@@ -7,6 +7,10 @@ from migen.fhdl.tracer import get_obj_var_name
 from migen.fhdl.verilog import _printexpr as verilog_printexpr
 
 
+__all__ = ["TSTriple", "Instance", "Memory",
+    "READ_FIRST", "WRITE_FIRST", "NO_CHANGE"]
+
+
 class Special(HUID):
     def iter_expressions(self):
         for x in []:
@@ -171,6 +175,7 @@ class Instance(Special):
             r += ");\n\n"
         return r
 
+
 (READ_FIRST, WRITE_FIRST, NO_CHANGE) = range(3)
 
 
@@ -319,7 +324,7 @@ class Memory(Special):
             memory_filename = add_data_file(gn(memory) + ".init", content)
 
             r += "initial begin\n"
-            r += "$readmemh(\"" + memory_filename + "\", " + gn(memory) + ");\n"
+            r += "\t$readmemh(\"" + memory_filename + "\", " + gn(memory) + ");\n"
             r += "end\n\n"
 
 
diff --git a/migen/fhdl/std.py b/migen/fhdl/std.py
deleted file mode 100644
index 76b1b3780..000000000
--- a/migen/fhdl/std.py
+++ /dev/null
@@ -1,7 +0,0 @@
-from migen.fhdl.structure import *
-from migen.fhdl.module import Module, FinalizeError
-from migen.fhdl.specials import TSTriple, Instance, Memory
-from migen.fhdl.bitcontainer import log2_int, bits_for, flen, fiter, fslice, freversed
-from migen.fhdl.decorators import DecorateModule, InsertCE, InsertReset, RenameClockDomains
-from migen.fhdl.decorators import (CEInserter, ResetInserter,
-    ClockDomainsRenamer, ModuleTransformer)
diff --git a/migen/genlib/cdc.py b/migen/genlib/cdc.py
index caa0ec4bb..860a504f4 100644
--- a/migen/genlib/cdc.py
+++ b/migen/genlib/cdc.py
@@ -1,7 +1,7 @@
-from migen.fhdl.std import *
-from migen.fhdl.bitcontainer import value_bits_sign
+from migen.fhdl.structure import *
+from migen.fhdl.module import Module
 from migen.fhdl.specials import Special
-from migen.fhdl.tools import list_signals
+from migen.fhdl.bitcontainer import value_bits_sign
 
 
 class NoRetiming(Special):
diff --git a/migen/genlib/coding.py b/migen/genlib/coding.py
index 5d1231e99..6327b3881 100644
--- a/migen/genlib/coding.py
+++ b/migen/genlib/coding.py
@@ -1,9 +1,10 @@
-from migen.fhdl.std import *
-
 """
 Encoders and decoders between binary and one-hot representation
 """
 
+from migen.fhdl.structure import *
+from migen.fhdl.module import Module
+
 
 class Encoder(Module):
     """Encode one-hot to binary
diff --git a/migen/genlib/divider.py b/migen/genlib/divider.py
index cb1426cf8..f31c7407b 100644
--- a/migen/genlib/divider.py
+++ b/migen/genlib/divider.py
@@ -1,4 +1,5 @@
-from migen.fhdl.std import *
+from migen.fhdl.structure import *
+from migen.fhdl.module import Module
 
 
 class Divider(Module):
diff --git a/migen/genlib/fifo.py b/migen/genlib/fifo.py
index 06b2359c7..33c984b8b 100644
--- a/migen/genlib/fifo.py
+++ b/migen/genlib/fifo.py
@@ -1,4 +1,6 @@
-from migen.fhdl.std import *
+from migen.fhdl.structure import *
+from migen.fhdl.module import Module
+from migen.fhdl.specials import Memory
 from migen.genlib.cdc import NoRetiming, MultiReg, GrayCounter
 from migen.genlib.record import layout_len, Record
 
diff --git a/migen/genlib/fsm.py b/migen/genlib/fsm.py
index 7a2ee6190..52451145b 100644
--- a/migen/genlib/fsm.py
+++ b/migen/genlib/fsm.py
@@ -1,11 +1,14 @@
 from collections import OrderedDict
 
-from migen.fhdl.std import *
-from migen.fhdl.module import FinalizeError
+from migen.fhdl.structure import *
+from migen.fhdl.module import Module, FinalizeError
 from migen.fhdl.visit import NodeTransformer
 from migen.fhdl.bitcontainer import value_bits_sign
 
 
+__all__ = ["AnonymousState", "NextState", "NextValue", "FSM"]
+
+
 class AnonymousState:
     pass
 
diff --git a/migen/genlib/io.py b/migen/genlib/io.py
index a26a1d990..db1cfdef0 100644
--- a/migen/genlib/io.py
+++ b/migen/genlib/io.py
@@ -1,6 +1,6 @@
-from migen.fhdl.std import *
+from migen.fhdl.structure import *
+from migen.fhdl.module import Module
 from migen.fhdl.specials import Special
-from migen.fhdl.tools import list_signals
 
 
 class DifferentialInput(Special):
diff --git a/migen/genlib/misc.py b/migen/genlib/misc.py
index aa610da3d..effdd16ea 100644
--- a/migen/genlib/misc.py
+++ b/migen/genlib/misc.py
@@ -1,4 +1,5 @@
-from migen.fhdl.std import *
+from migen.fhdl.structure import *
+from migen.fhdl.module import Module
 
 
 def split(v, *counts):
diff --git a/migen/genlib/record.py b/migen/genlib/record.py
index 238c9140d..bf6aa6197 100644
--- a/migen/genlib/record.py
+++ b/migen/genlib/record.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen.fhdl.structure import *
 from migen.fhdl.tracer import get_obj_var_name
 
 from functools import reduce
diff --git a/migen/genlib/resetsync.py b/migen/genlib/resetsync.py
index 2f635771f..3d46565c5 100644
--- a/migen/genlib/resetsync.py
+++ b/migen/genlib/resetsync.py
@@ -1,6 +1,5 @@
-from migen.fhdl.std import *
+from migen.fhdl.structure import *
 from migen.fhdl.specials import Special
-from migen.fhdl.tools import list_signals
 
 
 class AsyncResetSynchronizer(Special):
diff --git a/migen/genlib/roundrobin.py b/migen/genlib/roundrobin.py
index 5dd56759d..87ac5bb6f 100644
--- a/migen/genlib/roundrobin.py
+++ b/migen/genlib/roundrobin.py
@@ -1,4 +1,6 @@
-from migen.fhdl.std import *
+from migen.fhdl.structure import *
+from migen.fhdl.module import Module
+
 
 (SP_WITHDRAW, SP_CE) = range(2)
 
diff --git a/migen/genlib/sort.py b/migen/genlib/sort.py
index 9292c6d72..8f38e6292 100644
--- a/migen/genlib/sort.py
+++ b/migen/genlib/sort.py
@@ -1,4 +1,5 @@
-from migen.fhdl.std import *
+from migen.fhdl.structure import *
+from migen.fhdl.module import Module
 
 
 class BitonicSort(Module):
diff --git a/migen/sim.py b/migen/sim.py
index 96ca34768..8fda14ded 100644
--- a/migen/sim.py
+++ b/migen/sim.py
@@ -1,11 +1,14 @@
 import operator
 from collections import defaultdict
 
-from migen.fhdl.std import *
+from migen.fhdl.structure import *
 from migen.fhdl.structure import _Operator, _Assign, _Fragment
 from migen.fhdl.tools import list_inputs
 
 
+__all__ = ["Simulator"]
+
+
 class ClockState:
     def __init__(self, period, times_before_tick):
         self.period = period
diff --git a/migen/test/support.py b/migen/test/support.py
index 8982079ae..66c141bf2 100644
--- a/migen/test/support.py
+++ b/migen/test/support.py
@@ -1,5 +1,4 @@
-from migen.fhdl.std import *
-from migen.sim import Simulator
+from migen import *
 from migen.fhdl import verilog
 
 
diff --git a/migen/test/test_coding.py b/migen/test/test_coding.py
index d5d912728..4cbca1788 100644
--- a/migen/test/test_coding.py
+++ b/migen/test/test_coding.py
@@ -1,6 +1,6 @@
 import unittest
 
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.coding import *
 
 from migen.test.support import SimCase, SimBench
diff --git a/migen/test/test_fifo.py b/migen/test/test_fifo.py
index b798a6ae8..f0c1b105c 100644
--- a/migen/test/test_fifo.py
+++ b/migen/test/test_fifo.py
@@ -1,6 +1,6 @@
 import unittest
 
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.fifo import SyncFIFO
 
 from migen.test.support import SimCase, SimBench
diff --git a/migen/test/test_signed.py b/migen/test/test_signed.py
index 5a4b09b4d..9f0658279 100644
--- a/migen/test/test_signed.py
+++ b/migen/test/test_signed.py
@@ -1,6 +1,6 @@
 import unittest
 
-from migen.fhdl.std import *
+from migen import *
 from migen.test.support import SimCase
 
 
diff --git a/migen/test/test_size.py b/migen/test/test_size.py
index 0e7a493e0..2c29116a2 100644
--- a/migen/test/test_size.py
+++ b/migen/test/test_size.py
@@ -1,6 +1,6 @@
 import unittest
 
-from migen.fhdl.std import *
+from migen import *
 
 
 def _same_slices(a, b):
diff --git a/migen/test/test_sort.py b/migen/test/test_sort.py
index 835b4c071..13227528f 100644
--- a/migen/test/test_sort.py
+++ b/migen/test/test_sort.py
@@ -1,7 +1,7 @@
 import unittest
 from random import randrange
 
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.sort import *
 
 from migen.test.support import SimCase
diff --git a/migen/test/test_syntax.py b/migen/test/test_syntax.py
index 4ce80aefb..5ca721ae5 100644
--- a/migen/test/test_syntax.py
+++ b/migen/test/test_syntax.py
@@ -2,7 +2,7 @@ import unittest
 import subprocess
 import os
 
-from migen.fhdl.std import *
+from migen import *
 from migen.fhdl.verilog import convert