diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index f6567fa64..e957aa75b 100644
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -1433,7 +1433,7 @@ class LiteXSoC(SoC):
         # Timing constraints
         eth_rx_clk = getattr(phy, "crg", phy).cd_eth_rx.clk
         eth_tx_clk = getattr(phy, "crg", phy).cd_eth_tx.clk
-        if not isinstance(phy, LiteEthPHYModel):
+        if not isinstance(phy, LiteEthPHYModel) and not getattr(phy, "model", False):
             self.platform.add_period_constraint(eth_rx_clk, 1e9/phy.rx_clk_freq)
             self.platform.add_period_constraint(eth_tx_clk, 1e9/phy.tx_clk_freq)
             self.platform.add_false_path_constraints(self.crg.cd_sys.clk, eth_rx_clk, eth_tx_clk)
@@ -1485,7 +1485,7 @@ class LiteXSoC(SoC):
         # Timing constraints
         eth_rx_clk = getattr(phy, "crg", phy).cd_eth_rx.clk
         eth_tx_clk = getattr(phy, "crg", phy).cd_eth_tx.clk
-        if not isinstance(phy, LiteEthPHYModel):
+        if not isinstance(phy, LiteEthPHYModel) and not getattr(phy, "model", False):
             self.platform.add_period_constraint(eth_rx_clk, 1e9/phy.rx_clk_freq)
             self.platform.add_period_constraint(eth_tx_clk, 1e9/phy.tx_clk_freq)
             self.platform.add_false_path_constraints(self.crg.cd_sys.clk, eth_rx_clk, eth_tx_clk)