From 5346c3684f42dbe4b6c3b9fc87f5ac1e55d7cede Mon Sep 17 00:00:00 2001
From: Tom Keddie <git@bronwenandtom.com>
Date: Mon, 10 Jun 2019 08:33:02 -0700
Subject: [PATCH] boards/arty : Add directly connected spi clk pin to avoid
 need for STARTUPE2

---
 litex/boards/platforms/arty.py | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/litex/boards/platforms/arty.py b/litex/boards/platforms/arty.py
index aa38cf0a7..f03f9884a 100644
--- a/litex/boards/platforms/arty.py
+++ b/litex/boards/platforms/arty.py
@@ -79,13 +79,15 @@ _io = [
         IOStandard("LVCMOS33"),
     ),
 
-    ("spiflash4x", 0,  # clock needs to be accessed through STARTUPE2
+    ("spiflash4x", 0,
         Subsignal("cs_n", Pins("L13")),
+        Subsignal("clk", Pins("L16")),
         Subsignal("dq", Pins("K17", "K18", "L14", "M14")),
         IOStandard("LVCMOS33")
     ),
-    ("spiflash", 0,  # clock needs to be accessed through STARTUPE2
+    ("spiflash", 0,
         Subsignal("cs_n", Pins("L13")),
+        Subsignal("clk", Pins("L16")),
         Subsignal("mosi", Pins("K17")),
         Subsignal("miso", Pins("K18")),
         Subsignal("wp", Pins("L14")),