From 33f1c456bfcb919c2580c12c7add0635c222fe5c Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Mon, 6 Feb 2012 17:45:40 +0100 Subject: [PATCH] top: connect UART IRQ --- top.py | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/top.py b/top.py index 3a28d54bc..7014158ef 100644 --- a/top.py +++ b/top.py @@ -39,7 +39,11 @@ def get(): uart0 = uart.UART(0, clk_freq, baud=115200) csrcon0 = csr.Interconnect(wishbone2csr0.csr, [uart0.bank.interface]) - frag = autofragment.from_local() + interrupts = Fragment([ + cpu0.interrupt[0].eq(uart0.events.irq) + ]) + + frag = autofragment.from_local() + interrupts src_verilog, vns = verilog.convert(frag, {clkfx_sys.clkin, reset0.trigger_reset}, name="soc",