From 3465db25a7ed21ac19383d4d9410e179ce24a7fb Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 2 Mar 2015 11:55:28 +0100 Subject: [PATCH] soc/sdram: be more generic in naming --- misoclib/mem/sdram/phy/dfii.py | 4 +++- misoclib/soc/sdram.py | 39 +++++++++++++++++----------------- 2 files changed, 23 insertions(+), 20 deletions(-) diff --git a/misoclib/mem/sdram/phy/dfii.py b/misoclib/mem/sdram/phy/dfii.py index c3fa216f9..b4ec8f0c5 100644 --- a/misoclib/mem/sdram/phy/dfii.py +++ b/misoclib/mem/sdram/phy/dfii.py @@ -36,7 +36,9 @@ class PhaseInjector(Module, AutoCSR): self.sync += If(phase.rddata_valid, self._rddata.status.eq(phase.rddata)) class DFIInjector(Module, AutoCSR): - def __init__(self, a, ba, d, nphases=1): + def __init__(self, phy, a, ba): + d = phy.settings.dfi_d + nphases = phy.settings.nphases inti = dfi.Interface(a, ba, d, nphases) self.slave = dfi.Interface(a, ba, d, nphases) self.master = dfi.Interface(a, ba, d, nphases) diff --git a/misoclib/soc/sdram.py b/misoclib/soc/sdram.py index 62c9b70c9..5d033fb7e 100644 --- a/misoclib/soc/sdram.py +++ b/misoclib/soc/sdram.py @@ -1,17 +1,18 @@ from migen.fhdl.std import * from migen.bus import wishbone, csr +from migen.genlib.record import * from misoclib.mem.sdram.bus import dfi, lasmibus from misoclib.mem.sdram.phy import dfii from misoclib.mem.sdram.core import minicon, lasmicon -from misoclib.mem.sdram.core.lasmicon import crossbar +from misoclib.mem.sdram.core.lasmicon.crossbar import Crossbar from misoclib.mem.sdram.frontend import memtest, wishbone2lasmi from misoclib.soc import SoC, mem_decoder class SDRAMSoC(SoC): csr_map = { "dfii": 7, - "lasmicon": 8, + "controller": 8, "wishbone2lasmi": 9, "memtest_w": 10, "memtest_r": 11 @@ -39,24 +40,24 @@ class SDRAMSoC(SoC): self._sdram_phy_registered = True # DFI - self.submodules.dfii = dfii.DFIInjector(sdram_geom.mux_a, sdram_geom.bank_a, - phy.settings.dfi_d, phy.settings.nphases) - self.submodules.dficon0 = dfi.Interconnect(self.dfii.master, phy.dfi) + self.submodules.dfii = dfii.DFIInjector(phy, sdram_geom.mux_a, sdram_geom.bank_a) + self.comb += Record.connect(self.dfii.master, phy.dfi) # LASMICON if self.ramcon_type == "lasmicon": - self.submodules.lasmicon = lasmicon.LASMIcon(phy, sdram_geom, sdram_timing) - self.submodules.dficon1 = dfi.Interconnect(self.lasmicon.dfi, self.dfii.slave) + self.submodules.controller = controller = lasmicon.LASMIcon(phy, sdram_geom, sdram_timing) + self.comb += Record.connect(controller.dfi, self.dfii.slave) - self.submodules.lasmixbar = crossbar.Crossbar([self.lasmicon.lasmic], self.lasmicon.nrowbits) + self.submodules.crossbar = crossbar = Crossbar([controller.lasmic], controller.nrowbits) if self.with_memtest: - self.submodules.memtest_w = memtest.MemtestWriter(self.lasmixbar.get_master()) - self.submodules.memtest_r = memtest.MemtestReader(self.lasmixbar.get_master()) + self.submodules.memtest_w = memtest.MemtestWriter(crossbar.get_master()) + self.submodules.memtest_r = memtest.MemtestReader(crossbar.get_master()) if self.with_l2: - self.submodules.wishbone2lasmi = wishbone2lasmi.WB2LASMI(self.l2_size//4, self.lasmixbar.get_master()) - sdram_size = 2**self.lasmicon.lasmic.aw*self.lasmicon.lasmic.dw*self.lasmicon.lasmic.nbanks//8 + self.submodules.wishbone2lasmi = wishbone2lasmi.WB2LASMI(self.l2_size//4, crossbar.get_master()) + lasmic = self.controller.lasmic + sdram_size = 2**lasmic.aw*lasmic.dw*lasmic.nbanks//8 self.register_mem("sdram", self.mem_map["sdram"], self.wishbone2lasmi.wishbone, sdram_size) # MINICON @@ -64,18 +65,18 @@ class SDRAMSoC(SoC): if self.with_l2: raise ValueError("MINICON does not implement L2 cache (Use LASMICON or disable L2 cache (with_l2=False))") - self.submodules.minicon = sdramcon = minicon.Minicon(phy, sdram_geom, sdram_timing) - self.submodules.dficon1 = dfi.Interconnect(sdramcon.dfi, self.dfii.slave) - sdram_width = flen(sdramcon.bus.dat_r) + self.submodules.controller = controller = minicon.Minicon(phy, sdram_geom, sdram_timing) + self.comb += Record.connect(controller.dfi, self.dfii.slave) + sdram_width = flen(controller.bus.dat_r) sdram_size = 2**(sdram_geom.bank_a+sdram_geom.row_a+sdram_geom.col_a)*sdram_width//8 if sdram_width == 32: - self.register_mem("sdram", self.mem_map["sdram"], sdramcon.bus, sdram_size) + self.register_mem("sdram", self.mem_map["sdram"], controller.bus, sdram_size) elif sdram_width < 32: - self.submodules.dc = wishbone.DownConverter(32, sdram_width) - self.submodules.intercon = wishbone.InterconnectPointToPoint(self.dc.wishbone_o, sdramcon.bus) - self.register_mem("sdram", self.mem_map["sdram"], self.dc.wishbone_i, sdram_size) + self.submodules.downconverter = downconverter = wishbone.DownConverter(32, sdram_width) + self.comb += Record.connect(downconverter.wishbone_o, controller.bus) + self.register_mem("sdram", self.mem_map["sdram"], downconverter.wishbone_i, sdram_size) else: raise NotImplementedError("Unsupported SDRAM width of {} > 32".format(sdram_width)) else: