diff --git a/litex/soc/integration/common.py b/litex/soc/integration/common.py
index 3a56ffa7e..695e56090 100644
--- a/litex/soc/integration/common.py
+++ b/litex/soc/integration/common.py
@@ -83,6 +83,11 @@ class SoCMemRegion:
         self.length = length
         self.type   = type
 
+    def __str__(self):
+        return "<SoCMemRegion 0x{:x} 0x{:x} {}>".format(
+            self.origin, self.length, self.type)
+
+
 class SoCCSRRegion:
     def __init__(self, origin, busword, obj):
         self.origin  = origin
diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py
index b9e7b7bc8..346175f0c 100644
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@@ -401,7 +401,11 @@ class SoCCore(Module):
         self.mem_regions[name] = SoCMemRegion(origin, length, type)
         overlap = self.check_regions_overlap(self.mem_regions)
         if overlap is not None:
-            raise ValueError("Memory region conflict between {} and {}".format(overlap[0], overlap[1]))
+            o0, o1 = overlap[0], overlap[1]
+            raise ValueError("Memory region conflict between {} ({}) and {} ({})".format(
+                o0, self.mem_regions[o0],
+                o1, self.mem_regions[o1],
+            ))
 
     def register_mem(self, name, address, interface, size=0x10000000):
         self.add_wb_slave(address, interface, size)