From 3477aeaca1be51afa9ad9e4e534151b363a26e98 Mon Sep 17 00:00:00 2001
From: Richard Tucker <richard.tucker@motec.com.au>
Date: Thu, 19 Oct 2023 12:20:22 +1100
Subject: [PATCH] soc/cores/spi_mmap: add read only version register

---
 litex/soc/cores/spi/spi_mmap.py | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/litex/soc/cores/spi/spi_mmap.py b/litex/soc/cores/spi/spi_mmap.py
index 663078c1f..24a054d60 100644
--- a/litex/soc/cores/spi/spi_mmap.py
+++ b/litex/soc/cores/spi/spi_mmap.py
@@ -245,6 +245,10 @@ class SPICtrl(LiteXModule):
         self.slot_controls = []
         self.slot_status   = []
 
+        version = "SPI0"
+        self._version = CSRStatus(size=32, description="""SPI Module Version.""",
+            reset=int.from_bytes(str.encode(version), 'little'))
+
         # Create TX/RX Control/Status registers.
         self.tx_control  = CSRStorage(fields=[
             CSRField("enable", size=1, offset=0, values=[