From 34b45e36184340e67f419eaa00c61d68c64de1fc Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Thu, 11 Feb 2016 22:54:26 +0100
Subject: [PATCH] gen/build: use verilog 2001-style synthesis attributes for
 vivado (will need rework)

---
 litex/build/xilinx/common.py | 7 +++----
 litex/gen/fhdl/structure.py  | 5 +++--
 litex/gen/fhdl/verilog.py    | 9 ++++++---
 3 files changed, 12 insertions(+), 9 deletions(-)

diff --git a/litex/build/xilinx/common.py b/litex/build/xilinx/common.py
index 69c153846..2fdb9454a 100644
--- a/litex/build/xilinx/common.py
+++ b/litex/build/xilinx/common.py
@@ -44,7 +44,7 @@ def settings(path, ver=None, sub=None):
 
 class XilinxNoRetimingImpl(Module):
     def __init__(self, reg):
-        self.specials += SynthesisDirective("attribute register_balancing of {r} is no", r=reg)
+        reg.attribute += " OPTIMIZE =\"OFF\"," # XXX "register balancing is no" equivalent?
 
 
 class XilinxNoRetiming:
@@ -52,12 +52,11 @@ class XilinxNoRetiming:
     def lower(dr):
         return XilinxNoRetimingImpl(dr.reg)
 
-
 class XilinxMultiRegImpl(MultiRegImpl):
     def __init__(self, *args, **kwargs):
         MultiRegImpl.__init__(self, *args, **kwargs)
-        self.specials += [SynthesisDirective("attribute shreg_extract of {r} is no", r=r)
-            for r in self.regs]
+        for reg in self.regs:
+            reg.attribute += " SHIFT_EXTRACT=\"NO\", ASYNC_REG=\"TRUE\","
 
 
 class XilinxMultiReg:
diff --git a/litex/gen/fhdl/structure.py b/litex/gen/fhdl/structure.py
index 113954bfc..3316571d7 100644
--- a/litex/gen/fhdl/structure.py
+++ b/litex/gen/fhdl/structure.py
@@ -310,7 +310,7 @@ class Signal(_Value):
         defaults to 0) and `max` (exclusive, defaults to 2).
     related : Signal or None
     """
-    def __init__(self, bits_sign=None, name=None, variable=False, reset=0, name_override=None, min=None, max=None, related=None):
+    def __init__(self, bits_sign=None, name=None, variable=False, reset=0, name_override=None, min=None, max=None, related=None, attribute=""):
         from litex.gen.fhdl.bitcontainer import bits_for
 
         _Value.__init__(self)
@@ -339,6 +339,7 @@ class Signal(_Value):
         self.name_override = name_override
         self.backtrace = _tracer.trace_back(name)
         self.related = related
+        self.attribute = attribute
 
     def __setattr__(self, k, v):
         if k == "reset":
@@ -524,7 +525,7 @@ class Case(_Statement):
         for k, v in cases.items():
             if isinstance(k, (bool, int)):
                 k = Constant(k)
-            if (not isinstance(k, Constant) 
+            if (not isinstance(k, Constant)
                     and not (isinstance(k, str) and k == "default")):
                 raise TypeError("Case object is not a Migen constant")
             if not isinstance(v, _collections.Iterable):
diff --git a/litex/gen/fhdl/verilog.py b/litex/gen/fhdl/verilog.py
index bb0c4443b..1dc4635cb 100644
--- a/litex/gen/fhdl/verilog.py
+++ b/litex/gen/fhdl/verilog.py
@@ -196,13 +196,16 @@ def _printheader(f, ios, name, ns,
             r += "\tinput " + _printsig(ns, sig)
     r += "\n);\n\n"
     for sig in sorted(sigs - ios, key=lambda x: x.duid):
+        attributes = ""
+        if sig.attribute != "":
+            attributes = "(*" + sig.attribute[:-1] + "*) "
         if sig in wires:
-            r += "wire " + _printsig(ns, sig) + ";\n"
+            r += attributes + "wire " + _printsig(ns, sig) + ";\n"
         else:
             if reg_initialization:
-                r += "reg " + _printsig(ns, sig) + " = " + _printexpr(ns, sig.reset)[0] + ";\n"
+                r += attributes + "reg " + _printsig(ns, sig) + " = " + _printexpr(ns, sig.reset)[0] + ";\n"
             else:
-                r += "reg " + _printsig(ns, sig) + ";\n"
+                r += attributes + "reg " + _printsig(ns, sig) + ";\n"
     r += "\n"
     return r