From 34ce6b077f4e3bdcc1519b441b3dc437f8060a33 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Mon, 21 Sep 2015 21:19:58 +0800 Subject: [PATCH] verilog: remove unneeded import --- migen/fhdl/verilog.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py index 009c7e1ff..d5d878c9b 100644 --- a/migen/fhdl/verilog.py +++ b/migen/fhdl/verilog.py @@ -5,7 +5,7 @@ from migen.fhdl.structure import * from migen.fhdl.structure import _Operator, _Slice, _Assign, _Fragment from migen.fhdl.tools import * from migen.fhdl.bitcontainer import bits_for, flen -from migen.fhdl.namer import Namespace, build_namespace +from migen.fhdl.namer import build_namespace from migen.fhdl.conv_output import ConvOutput