From 35929c0f8a8f1cc098a6b6ebb569caca8df8c08d Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 14 Aug 2020 15:29:49 +0200
Subject: [PATCH] soc/integration/csr_bridge: use registered version only when
 SDRAM is present.

Seems to be a good compromise for now.
---
 litex/soc/integration/soc.py      | 9 +++++++--
 litex/soc/integration/soc_core.py | 3 ---
 2 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index ad216377a..54f969c91 100644
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -803,7 +803,7 @@ class SoC(Module):
     def add_rom(self, name, origin, size, contents=[]):
         self.add_ram(name, origin, size, contents, mode="r")
 
-    def add_csr_bridge(self, origin):
+    def add_csr_bridge(self, origin, register=False):
         csr_bridge_cls = {
             "wishbone": wishbone.Wishbone2CSR,
             "axi-lite": axi.AXILite2CSR,
@@ -811,7 +811,8 @@ class SoC(Module):
         self.submodules.csr_bridge = csr_bridge_cls(
             bus_csr       = csr_bus.Interface(
             address_width = self.csr.address_width,
-            data_width    = self.csr.data_width))
+            data_width    = self.csr.data_width),
+            register = register)
         csr_size   = 2**(self.csr.address_width + 2)
         csr_region = SoCRegion(origin=origin, size=csr_size, cached=False)
         bus = getattr(self.csr_bridge, self.bus.standard.replace('-', '_'))
@@ -910,6 +911,10 @@ class SoC(Module):
             "axi-lite": axi.AXILiteInterconnectShared,
         }[self.bus.standard]
 
+        # SoC CSR bridge ---------------------------------------------------------------------------
+        # FIXME: for now, use registered CSR bridge when SDRAM is present; find the best compromise.
+        self.add_csr_bridge(self.mem_map["csr"], register=hasattr(self, "sdram"))
+
         # SoC Bus Interconnect ---------------------------------------------------------------------
         if len(self.bus.masters) and len(self.bus.slaves):
             # If 1 bus_master, 1 bus_slave and no address translation, use InterconnectPointToPoint.
diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py
index 281f34e4e..607413222 100644
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@@ -187,9 +187,6 @@ class SoCCore(LiteXSoC):
             if timer_uptime:
                 self.timer0.add_uptime()
 
-        # Add CSR bridge
-        self.add_csr_bridge(self.mem_map["csr"])
-
     # Methods --------------------------------------------------------------------------------------
 
     def add_interrupt(self, interrupt_name, interrupt_id=None, use_loc_if_exists=False):