From 68eeba918186f5bd3d3f4e0552b286f7db08d5a3 Mon Sep 17 00:00:00 2001
From: Arnaud Durand <arnaud.durand@unifr.ch>
Date: Thu, 4 Jul 2019 00:58:26 +0200
Subject: [PATCH] Add verilog submodule from CPU cores to manifest

---
 MANIFEST.in | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/MANIFEST.in b/MANIFEST.in
index 26d681702..a15c845d9 100644
--- a/MANIFEST.in
+++ b/MANIFEST.in
@@ -1,5 +1,8 @@
 graft litex/build/sim
 graft litex/soc/software
 graft litex/soc/cores/cpu/lm32/verilog
+graft litex/soc/cores/cpu/minerva/verilog
 graft litex/soc/cores/cpu/mor1kx/verilog
-graft litex/soc/cores/cpu/picorv32/verilog
\ No newline at end of file
+graft litex/soc/cores/cpu/picorv32/verilog
+graft litex/soc/cores/cpu/rocket/verilog
+graft litex/soc/cores/cpu/vexriscv/verilog