From 360c849f21f4b976762a059ac34178e2a0affe77 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 9 Mar 2015 12:45:46 +0100 Subject: [PATCH] liteeth: fix cnt_inc in IDLE state (we should wait sop to inc counter) --- misoclib/com/liteeth/mac/frontend/sram.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/misoclib/com/liteeth/mac/frontend/sram.py b/misoclib/com/liteeth/mac/frontend/sram.py index 7df9c5848..cb6a4d72c 100644 --- a/misoclib/com/liteeth/mac/frontend/sram.py +++ b/misoclib/com/liteeth/mac/frontend/sram.py @@ -69,10 +69,10 @@ class LiteEthMACSRAMWriter(Module, AutoCSR): self.submodules += fsm fsm.act("IDLE", - inc_cnt.eq(sink.stb), If(sink.stb & sink.sop, - ongoing.eq(1), If(fifo.sink.ack, + ongoing.eq(1), + inc_cnt.eq(1), NextState("WRITE") ) )