From c77da3a8bc4a119869cf931a1a769957b7f7d083 Mon Sep 17 00:00:00 2001 From: Gabriel Somlo Date: Wed, 23 Sep 2020 14:16:14 -0400 Subject: [PATCH] RFC: json2dts: set CPU clock-frequency and SoC bus-frequency FIXME: timebase-frequency isn't to be used as the raw CPU clock, so on vexriscv we might want to re-evaluate also setting *that* to the `CONFIG_CLOCK_FREQUENCY`. Decide whether to keep the SoC's `bus-frequency` cell, or whether to go with the CPU's `clock-frequency` only. --- litex/tools/litex_json2dts.py | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/litex/tools/litex_json2dts.py b/litex/tools/litex_json2dts.py index d0de5ae20..93d65278a 100755 --- a/litex/tools/litex_json2dts.py +++ b/litex/tools/litex_json2dts.py @@ -56,7 +56,7 @@ def generate_dts(d): #size-cells = <0>; timebase-frequency = <{sys_clk_freq}>; cpu@0 {{ - clock-frequency = <0x0>; + clock-frequency = <{sys_clk_freq}>; compatible = "spinalhdl,vexriscv", "sifive,rocket0", "riscv"; d-cache-block-size = <0x40>; d-cache-sets = <0x40>; @@ -128,9 +128,10 @@ def generate_dts(d): soc { #address-cells = <1>; #size-cells = <1>; + bus-frequency = <{sys_clk_freq}>; compatible = "simple-bus"; ranges; -""" +""".format(sys_clk_freq=d["constants"]["config_clock_frequency"]) # Interrupt controller -----------------------------------------------------------------------------