diff --git a/litex/soc/cores/cpu/cv32e40p/core.py b/litex/soc/cores/cpu/cv32e40p/core.py index 99883d7da..80d5bba3f 100644 --- a/litex/soc/cores/cpu/cv32e40p/core.py +++ b/litex/soc/cores/cpu/cv32e40p/core.py @@ -22,15 +22,15 @@ CPU_VARIANTS = ["standard", "full"] # GCC Flags ---------------------------------------------------------------------------------------- GCC_FLAGS = { - # /-------- Base ISA - # |/------- Hardware Multiply + Divide - # ||/----- Atomics - # |||/---- Compressed ISA - # ||||/--- Single-Precision Floating-Point - # |||||/-- Double-Precision Floating-Point - # imacfd - "standard": "-march=rv32imc -mabi=ilp32 ", - "full": "-march=rv32imfc -mabi=ilp32 ", + # /------------ Base ISA + # | /------- Hardware Multiply + Divide + # | |/----- Atomics + # | ||/---- Compressed ISA + # | |||/--- Single-Precision Floating-Point + # | ||||/-- Double-Precision Floating-Point + # i macfd + "standard": "-march=rv32i2p0_mc -mabi=ilp32 ", + "full": "-march=rv32i2p0_mfc -mabi=ilp32 ", } # OBI / APB / Trace Layouts ------------------------------------------------------------------------ diff --git a/litex/soc/cores/cpu/cv32e41p/core.py b/litex/soc/cores/cpu/cv32e41p/core.py index d0fd6561a..98b3e1a18 100644 --- a/litex/soc/cores/cpu/cv32e41p/core.py +++ b/litex/soc/cores/cpu/cv32e41p/core.py @@ -22,14 +22,14 @@ CPU_VARIANTS = ["standard"] # GCC Flags ---------------------------------------------------------------------------------------- GCC_FLAGS = { - # /-------- Base ISA - # |/------- Hardware Multiply + Divide - # ||/----- Atomics - # |||/---- Compressed ISA - # ||||/--- Single-Precision Floating-Point - # |||||/-- Double-Precision Floating-Point - # imacfd - "standard": "-march=rv32imc -mabi=ilp32 ", + # /------------ Base ISA + # | /------- Hardware Multiply + Divide + # | |/----- Atomics + # | ||/---- Compressed ISA + # | |||/--- Single-Precision Floating-Point + # | ||||/-- Double-Precision Floating-Point + # i macfd + "standard": "-march=rv32i2p0_mc -mabi=ilp32 ", } # OBI / APB / Trace Layouts ------------------------------------------------------------------------ diff --git a/litex/soc/cores/cpu/cva5/core.py b/litex/soc/cores/cpu/cva5/core.py index af6b5dce4..b69d9d900 100644 --- a/litex/soc/cores/cpu/cva5/core.py +++ b/litex/soc/cores/cpu/cva5/core.py @@ -20,15 +20,15 @@ CPU_VARIANTS = ["minimal", "standard"] # GCC Flags ---------------------------------------------------------------------------------------- GCC_FLAGS = { - # /-------- Base ISA - # |/------- Hardware Multiply + Divide - # ||/----- Atomics - # |||/---- Compressed ISA - # ||||/--- Single-Precision Floating-Point - # |||||/-- Double-Precision Floating-Point - # imacfd - "minimal" : "-march=rv32i -mabi=ilp32 ", - "standard" : "-march=rv32im -mabi=ilp32 ", + # /------------ Base ISA + # | /------- Hardware Multiply + Divide + # | |/----- Atomics + # | ||/---- Compressed ISA + # | |||/--- Single-Precision Floating-Point + # | ||||/-- Double-Precision Floating-Point + # i macfd + "minimal" : "-march=rv32i2p0 -mabi=ilp32 ", + "standard" : "-march=rv32i2p0_m -mabi=ilp32 ", } # CVA5 ---------------------------------------------------------------------------------------------- diff --git a/litex/soc/cores/cpu/femtorv/core.py b/litex/soc/cores/cpu/femtorv/core.py index fbb3d6a31..2d85e8857 100644 --- a/litex/soc/cores/cpu/femtorv/core.py +++ b/litex/soc/cores/cpu/femtorv/core.py @@ -26,20 +26,20 @@ CPU_VARIANTS = { # GCC Flags ---------------------------------------------------------------------------------------- GCC_FLAGS = { - # /-------- Base ISA - # |/------- Hardware Multiply + Divide - # ||/----- Atomics - # |||/---- Compressed ISA - # ||||/--- Single-Precision Floating-Point - # |||||/-- Double-Precision Floating-Point - # imacfd - "standard": "-march=rv32i -mabi=ilp32", - "quark": "-march=rv32i -mabi=ilp32", - "tachyon": "-march=rv32i -mabi=ilp32", - "electron": "-march=rv32im -mabi=ilp32", - "intermissum": "-march=rv32im -mabi=ilp32", - "gracilis": "-march=rv32imc -mabi=ilp32", - "petitbateau": "-march=rv32imfc -mabi=ilp32f", + # /------------ Base ISA + # | /------- Hardware Multiply + Divide + # | |/----- Atomics + # | ||/---- Compressed ISA + # | |||/--- Single-Precision Floating-Point + # | ||||/-- Double-Precision Floating-Point + # i macfd + "standard": "-march=rv32i2p0 -mabi=ilp32", + "quark": "-march=rv32i2p0 -mabi=ilp32", + "tachyon": "-march=rv32i2p0 -mabi=ilp32", + "electron": "-march=rv32i2p0_m -mabi=ilp32", + "intermissum": "-march=rv32i2p0_m -mabi=ilp32", + "gracilis": "-march=rv32i2p0_mc -mabi=ilp32", + "petitbateau": "-march=rv32i2p0_mfc -mabi=ilp32f", } # FemtoRV ------------------------------------------------------------------------------------------ diff --git a/litex/soc/cores/cpu/firev/core.py b/litex/soc/cores/cpu/firev/core.py index 2439d5190..048bf85ab 100644 --- a/litex/soc/cores/cpu/firev/core.py +++ b/litex/soc/cores/cpu/firev/core.py @@ -20,14 +20,14 @@ CPU_VARIANTS = { # GCC Flags ---------------------------------------------------------------------------------------- GCC_FLAGS = { - # /-------- Base ISA - # |/------- Hardware Multiply + Divide - # ||/----- Atomics - # |||/---- Compressed ISA - # ||||/--- Single-Precision Floating-Point - # |||||/-- Double-Precision Floating-Point - # imacfd - "standard": "-march=rv32i -mabi=ilp32", + # /------------ Base ISA + # | /------- Hardware Multiply + Divide + # | |/----- Atomics + # | ||/---- Compressed ISA + # | |||/--- Single-Precision Floating-Point + # | ||||/-- Double-Precision Floating-Point + # i macfd + "standard": "-march=rv32i2p0 -mabi=ilp32", } # FireV ------------------------------------------------------------------------------------------ diff --git a/litex/soc/cores/cpu/ibex/core.py b/litex/soc/cores/cpu/ibex/core.py index f1346e755..b84a6a751 100644 --- a/litex/soc/cores/cpu/ibex/core.py +++ b/litex/soc/cores/cpu/ibex/core.py @@ -22,14 +22,14 @@ CPU_VARIANTS = ["standard"] # GCC Flags ---------------------------------------------------------------------------------------- GCC_FLAGS = { - # /-------- Base ISA - # |/------- Hardware Multiply + Divide - # ||/----- Atomics - # |||/---- Compressed ISA - # ||||/--- Single-Precision Floating-Point - # |||||/-- Double-Precision Floating-Point - # imacfd - "standard": "-march=rv32imc -mabi=ilp32 ", + # /------------ Base ISA + # | /------- Hardware Multiply + Divide + # | |/----- Atomics + # | ||/---- Compressed ISA + # | |||/--- Single-Precision Floating-Point + # | ||||/-- Double-Precision Floating-Point + # i macfd + "standard": "-march=rv32i2p0_mc -mabi=ilp32 ", } # OBI <> Wishbone ---------------------------------------------------------------------------------- diff --git a/litex/soc/cores/cpu/neorv32/core.py b/litex/soc/cores/cpu/neorv32/core.py index bc60b497f..7cd0ba0d0 100644 --- a/litex/soc/cores/cpu/neorv32/core.py +++ b/litex/soc/cores/cpu/neorv32/core.py @@ -20,17 +20,17 @@ CPU_VARIANTS = ["minimal", "lite", "standard", "full"] # GCC Flags ---------------------------------------------------------------------------------------- GCC_FLAGS = { - # /-------- Base ISA - # |/------- Hardware Multiply + Divide - # ||/----- Atomics - # |||/---- Compressed ISA - # ||||/--- Single-Precision Floating-Point - # |||||/-- Double-Precision Floating-Point - # imacfd - "minimal": "-march=rv32i -mabi=ilp32", - "lite": "-march=rv32imc -mabi=ilp32", - "standard": "-march=rv32imc -mabi=ilp32", - "full": "-march=rv32imc -mabi=ilp32", + # /------------ Base ISA + # | /------- Hardware Multiply + Divide + # | |/----- Atomics + # | ||/---- Compressed ISA + # | |||/--- Single-Precision Floating-Point + # | ||||/-- Double-Precision Floating-Point + # i macfd + "minimal": "-march=rv32i2p0 -mabi=ilp32", + "lite": "-march=rv32i2p0_mc -mabi=ilp32", + "standard": "-march=rv32i2p0_mc -mabi=ilp32", + "full": "-march=rv32i2p0_mc -mabi=ilp32", } # NEORV32 ------------------------------------------------------------------------------------------ diff --git a/litex/soc/cores/cpu/picorv32/core.py b/litex/soc/cores/cpu/picorv32/core.py index 96f124ab9..66cb3b99f 100644 --- a/litex/soc/cores/cpu/picorv32/core.py +++ b/litex/soc/cores/cpu/picorv32/core.py @@ -23,15 +23,15 @@ CPU_VARIANTS = ["minimal", "standard"] # GCC Flags ---------------------------------------------------------------------------------------- GCC_FLAGS = { - # /-------- Base ISA - # |/------- Hardware Multiply + Divide - # ||/----- Atomics - # |||/---- Compressed ISA - # ||||/--- Single-Precision Floating-Point - # |||||/-- Double-Precision Floating-Point - # imacfd - "minimal": "-march=rv32i -mabi=ilp32 ", - "standard": "-march=rv32im -mabi=ilp32 ", + # /------------ Base ISA + # | /------- Hardware Multiply + Divide + # | |/----- Atomics + # | ||/---- Compressed ISA + # | |||/--- Single-Precision Floating-Point + # | ||||/-- Double-Precision Floating-Point + # i macfd + "minimal": "-march=rv32i2p0 -mabi=ilp32 ", + "standard": "-march=rv32i2p0_m -mabi=ilp32 ", } # PicoRV32 ----------------------------------------------------------------------------------------- diff --git a/litex/soc/cores/cpu/serv/core.py b/litex/soc/cores/cpu/serv/core.py index 58e654b0b..8a0dff165 100644 --- a/litex/soc/cores/cpu/serv/core.py +++ b/litex/soc/cores/cpu/serv/core.py @@ -20,15 +20,15 @@ CPU_VARIANTS = ["standard", "mdu"] # GCC Flags ---------------------------------------------------------------------------------------- GCC_FLAGS = { - # /-------- Base ISA - # |/------- Hardware Multiply + Divide - # ||/----- Atomics - # |||/---- Compressed ISA - # ||||/--- Single-Precision Floating-Point - # |||||/-- Double-Precision Floating-Point - # imacfd - "standard": "-march=rv32i -mabi=ilp32", - "mdu": "-march=rv32im -mabi=ilp32", + # /------------ Base ISA + # | /------- Hardware Multiply + Divide + # | |/----- Atomics + # | ||/---- Compressed ISA + # | |||/--- Single-Precision Floating-Point + # | ||||/-- Double-Precision Floating-Point + # i macfd + "standard": "-march=rv32i2p0 -mabi=ilp32", + "mdu": "-march=rv32i2p0_m -mabi=ilp32", } # SERV ---------------------------------------------------------------------------------------------