diff --git a/litex/soc/cores/cpu/rocket/core.py b/litex/soc/cores/cpu/rocket/core.py
index 54c31596c..c9fdb0ddc 100644
--- a/litex/soc/cores/cpu/rocket/core.py
+++ b/litex/soc/cores/cpu/rocket/core.py
@@ -56,15 +56,17 @@ class RocketRV64(CPU):
     endianness           = "little"
     gcc_triple           = ("riscv64-unknown-elf")
     linker_output_format = "elf64-littleriscv"
-    io_regions           = {0x80000000: 0x80000000} # origin, length
+    io_regions           = {0x10000000: 0x70000000} # origin, length
 
     @property
     def mem_map(self):
         # Rocket reserves the first 256Mbytes for internal use, so we must change default mem_map.
         return {
-            "rom"  : 0x10000000,
-            "sram" : 0x11000000,
-            "csr"  : 0x92000000,
+            "rom"      : 0x10000000,
+            "sram"     : 0x11000000,
+            "csr"      : 0x12000000,
+            "ethmac"   : 0x30000000,
+            "main_ram" : 0x80000000,
         }
 
     @property
diff --git a/litex/soc/cores/cpu/rocket/verilog b/litex/soc/cores/cpu/rocket/verilog
index b17b6984b..d67a7d7a1 160000
--- a/litex/soc/cores/cpu/rocket/verilog
+++ b/litex/soc/cores/cpu/rocket/verilog
@@ -1 +1 @@
-Subproject commit b17b6984b9b7b0d0c259306ba94187abae7f37f5
+Subproject commit d67a7d7a12ff06297226b1862412849c4d50e949