From 37823e34b66954d401038fd7d8678e2052dfe963 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 21 Aug 2024 17:10:36 +0200 Subject: [PATCH] soc/cores/hyperbus: Simplify Clk Generation. --- litex/soc/cores/hyperbus.py | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/litex/soc/cores/hyperbus.py b/litex/soc/cores/hyperbus.py index 16dc8affe..3725c33f8 100644 --- a/litex/soc/cores/hyperbus.py +++ b/litex/soc/cores/hyperbus.py @@ -142,14 +142,11 @@ class HyperRAM(LiteXModule): # Burst Timer ------------------------------------------------------------------------------ self.burst_timer = burst_timer = WaitTimer(sys_clk_freq * self.tCSM) - # Clock Generation (sys_clk/4) ------------------------------------------------------------- + # Clk Generation --------------------------------------------------------------------------- self.sync_io += [ + clk_phase.eq(0b00), If(cs, - # Increment Clk Phase on CS. clk_phase.eq(clk_phase + 1) - ).Else( - # Else set Clk Phase to default value. - clk_phase.eq(0b00) ) ] cases = {