diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index 05b70af8a..fb1f95e48 100644
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -1366,7 +1366,7 @@ class LiteXSoC(SoC):
                     else:
                         self.logger.info("Converting MEM data width: {} to {} via Wishbone".format(
                             port.data_width,
-                            self.mem_bus.data_width))
+                            mem_bus.data_width))
                         # FIXME: Replace WB data-width converter with native AXI converter.
                         mem_wb  = wishbone.Interface(
                             data_width = self.cpu.mem_axi.data_width,