From 378c430dd0fd99ca0d410cbbfa3796d624b20bd3 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sat, 12 Feb 2022 21:47:08 +0100 Subject: [PATCH] soc/add_sdram: Fix typo when removing Rocket specific hardcoding. --- litex/soc/integration/soc.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index 05b70af8a..fb1f95e48 100644 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -1366,7 +1366,7 @@ class LiteXSoC(SoC): else: self.logger.info("Converting MEM data width: {} to {} via Wishbone".format( port.data_width, - self.mem_bus.data_width)) + mem_bus.data_width)) # FIXME: Replace WB data-width converter with native AXI converter. mem_wb = wishbone.Interface( data_width = self.cpu.mem_axi.data_width,