From 379d47a8437d7cfffe52223122c98f2b1b26d890 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Mon, 10 Feb 2020 17:02:20 +0100
Subject: [PATCH] soc/add_sdram: add sdram csr

---
 litex/soc/integration/soc.py       | 1 +
 litex/soc/integration/soc_sdram.py | 6 ------
 2 files changed, 1 insertion(+), 6 deletions(-)

diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index 464e3f92c..d4820261e 100755
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -905,6 +905,7 @@ class LiteXSoC(SoC):
             timing_settings = module.timing_settings,
             clk_freq        = self.sys_clk_freq,
             **kwargs)
+        self.csr.add("sdram")
 
         # LiteDRAM port ----------------------------------------------------------------------------
         port = self.sdram.crossbar.get_port()
diff --git a/litex/soc/integration/soc_sdram.py b/litex/soc/integration/soc_sdram.py
index e68fbd1fe..e72116cdf 100644
--- a/litex/soc/integration/soc_sdram.py
+++ b/litex/soc/integration/soc_sdram.py
@@ -18,12 +18,6 @@ __all__ = ["SoCSDRAM", "soc_sdram_args", "soc_sdram_argdict"]
 # SoCSDRAM -----------------------------------------------------------------------------------------
 
 class SoCSDRAM(SoCCore):
-    csr_map = {
-        "sdram":    8,
-        "l2_cache": 9,
-    }
-    csr_map.update(SoCCore.csr_map)
-
     def __init__(self, platform, clk_freq,
         l2_size           = 8192,
         l2_reverse        = True,