diff --git a/litex/gen/fhdl/verilog.py b/litex/gen/fhdl/verilog.py
index fe686f766..0de39d8d6 100644
--- a/litex/gen/fhdl/verilog.py
+++ b/litex/gen/fhdl/verilog.py
@@ -1,8 +1,8 @@
 #
-# This file is part of Migen and has been adapted/modified for LiteX.
+# This file is part of LiteX (Adapted from Migen for LiteX usage).
 #
 # This file is Copyright (c) 2013-2014 Sebastien Bourdeauducq <sb@m-labs.hk>
-# This file is Copyright (c) 2013-2018 Florent Kermarrec <florent@enjoy-digital.fr>
+# This file is Copyright (c) 2013-2021 Florent Kermarrec <florent@enjoy-digital.fr>
 # This file is Copyright (c) 2013-2017 Robert Jordens <jordens@gmail.com>
 # This file is Copyright (c) 2016-2018 whitequark <whitequark@whitequark.org>
 # This file is Copyright (c) 2017 Adam Greig <adam@adamgreig.com>