diff --git a/misoclib/mem/sdram/core/__init__.py b/misoclib/mem/sdram/core/__init__.py
index e74602705..7af08c1d5 100644
--- a/misoclib/mem/sdram/core/__init__.py
+++ b/misoclib/mem/sdram/core/__init__.py
@@ -19,7 +19,7 @@ class SDRAMCore(Module, AutoCSR):
 				controller_settings, **kwargs)
 			self.comb += Record.connect(controller.dfi, self.dfii.slave)
 
-			self.submodules.crossbar = crossbar = lasmixbar.LASMIxbar([controller.lasmic], controller.nrowbits)
+			self.submodules.crossbar = lasmixbar.LASMIxbar([controller.lasmic], controller.nrowbits)
 
 		# MINICON
 		elif isinstance(controller_settings, minicon.MiniconSettings):
diff --git a/misoclib/soc/sdram.py b/misoclib/soc/sdram.py
index a878727ac..3a8c5617f 100644
--- a/misoclib/soc/sdram.py
+++ b/misoclib/soc/sdram.py
@@ -1,12 +1,12 @@
 from migen.fhdl.std import *
-from migen.bus import wishbone, csr
+from migen.bus import wishbone
 from migen.genlib.record import *
 
 from misoclib.mem.sdram.core import SDRAMCore
 from misoclib.mem.sdram.core.lasmicon import LASMIconSettings
 from misoclib.mem.sdram.core.minicon import MiniconSettings
 from misoclib.mem.sdram.frontend import memtest, wishbone2lasmi
-from misoclib.soc import SoC, mem_decoder
+from misoclib.soc import SoC
 
 class SDRAMSoC(SoC):
 	csr_map = {
@@ -54,7 +54,7 @@ class SDRAMSoC(SoC):
 				self.submodules.memtest_r = memtest.MemtestReader(self.sdram.crossbar.get_master())
 
 			l2_size = self.sdram_controller_settings.l2_size
-			if l2_size != 0:
+			if l2_size:
 				# XXX Vivado 2014.X workaround, Vivado is not able to map correctly our L2 cache.
 				# Issue is reported to Xilinx and should be fixed in next releases (2015.1?).
 				# Remove this workaround when fixed by Xilinx.