From 622a35fd4e87f44ae39accb39da6af79137d26b2 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Fri, 30 Sep 2022 11:52:14 +0200 Subject: [PATCH] Improve naxriscv peripheral latency --- litex/soc/cores/cpu/naxriscv/core.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/litex/soc/cores/cpu/naxriscv/core.py b/litex/soc/cores/cpu/naxriscv/core.py index d857c63bb..bbdff09ef 100755 --- a/litex/soc/cores/cpu/naxriscv/core.py +++ b/litex/soc/cores/cpu/naxriscv/core.py @@ -123,8 +123,8 @@ class NaxRiscv(CPU): self.human_name = self.human_name self.reset = Signal() self.interrupt = Signal(32) - self.ibus = ibus = axi.AXILiteInterface(address_width=32, data_width=64) - self.dbus = dbus = axi.AXILiteInterface(address_width=32, data_width=64) + self.ibus = ibus = axi.AXILiteInterface(address_width=32, data_width=32) + self.dbus = dbus = axi.AXILiteInterface(address_width=32, data_width=32) self.periph_buses = [ibus, dbus] # Peripheral buses (Connected to main SoC's bus). self.memory_buses = [] # Memory buses (Connected directly to LiteDRAM). @@ -228,8 +228,8 @@ class NaxRiscv(CPU): ndir = os.path.join(vdir, "ext", "NaxRiscv") sdir = os.path.join(vdir, "ext", "SpinalHDL") - NaxRiscv.git_setup("NaxRiscv", ndir, "https://github.com/SpinalHDL/NaxRiscv.git" , "main", "cb2a598a") - NaxRiscv.git_setup("SpinalHDL", sdir, "https://github.com/SpinalHDL/SpinalHDL.git", "dev" , "a130f7b7") + NaxRiscv.git_setup("NaxRiscv", ndir, "https://github.com/SpinalHDL/NaxRiscv.git" , "main", "518d2713") + NaxRiscv.git_setup("SpinalHDL", sdir, "https://github.com/SpinalHDL/SpinalHDL.git", "dev" , "56400992") gen_args = [] gen_args.append(f"--netlist-name={NaxRiscv.netlist_name}")