From 38a8a171dd04d6c6a635709c651b098a94783902 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Tue, 2 Apr 2024 10:43:01 +0200
Subject: [PATCH] integration/builder: Replace soc_core's initialize_memory
 with optional "init_mems" method.

Make sure to also attach Builder to SoC to allow easily get/use builder properties in init_mems method.
---
 litex/soc/integration/builder.py  | 16 ++++++++----
 litex/soc/integration/soc_core.py | 42 -------------------------------
 2 files changed, 11 insertions(+), 47 deletions(-)

diff --git a/litex/soc/integration/builder.py b/litex/soc/integration/builder.py
index fbfe7673a..0e01155ee 100644
--- a/litex/soc/integration/builder.py
+++ b/litex/soc/integration/builder.py
@@ -92,7 +92,9 @@ class Builder:
         # Documentation.
         generate_doc     = False):
 
-        self.soc = soc
+        # SoC/Builder Attach.
+        self.soc         = soc   # Attach SoC to Builder.
+        self.soc.builder = self  # Attach Builder to SoC.
 
         # Directories.
         self.output_dir    = os.path.abspath(output_dir    or os.path.join("build", soc.platform.name))
@@ -388,12 +390,16 @@ class Builder:
                 self._prepare_rom_software()
                 self._generate_rom_software(compile_bios=use_bios)
 
-                # Allow soc to override the memory initialisation.
-                self.soc.initialize_memory(self.software_dir, **kwargs)
+                # Initialize Memories.
+                # Allow User Design to optionally initialize Memories through SoC.init_ram/init_rom.
+                if hasattr(self.soc, "init_mems"):
+                    self.soc.init_mems(**kwargs)
 
                 # Initialize ROM.
-                if use_bios and self.soc.integrated_rom_size and not getattr(self.soc, "rom").mem.init:
-                    self._initialize_rom_software()
+                if use_bios and self.soc.integrated_rom_size:
+                    # Only initialize if not already initialized.
+                    if not getattr(self.soc, "rom").mem.init:
+                        self._initialize_rom_software()
 
         # Translate compile_gateware to run.
         if "run" not in kwargs:
diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py
index 7e89c9c0d..34a430bfc 100644
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@@ -280,48 +280,6 @@ class SoCCore(LiteXSoC):
     def add_csr_region(self, name, origin, busword, obj):
         self.csr_regions[name] = SoCCSRRegion(origin, busword, obj)
 
-    def initialize_memory(self, software_dir, **kwargs):
-        """initialize_memory
-        The target SoC can implement this function to override the memory initialisation
-        during the build to load a program or data to main_ram and/or rom.
-
-        Parameters
-        ----------
-        software_dir : str
-            Builder software_dir where the soc libs and bios are built.
-
-        kwargs
-            Builder kwargs for any additional context if required
-.
-        Example:
-
-        class MySoC(SoCCore):
-            def __init__(self,
-                ...
-                self.add_config("MAIN_RAM_INIT") # firmware is in ram
-
-            def initialize_memory(self, software_dir, **kwargs):
-                if self.cpu_type is None:
-                    return
-
-                filename  = os.path.join(software_dir, "firmware", "firmware.bin")
-                data = get_mem_data(filename, endianness=self.cpu.endianness)
-                self.init_rom(name="main_ram", contents=data, auto_size=False)
-
-        def main():
-            ...
-
-            builder = Builder(soc, **parser.builder_argdict)
-
-            # add custom firmware: compiled by connecting here and stored in initialize_memory()
-            src="firmware"
-            src_dir = os.path.join(os.path.abspath(os.path.dirname(__file__)), src)
-            builder.add_software_package(src, src_dir)
-
-            builder.build(**parser.toolchain_argdict)
-        """
-        pass
-
 # SoCCore arguments --------------------------------------------------------------------------------
 
 def soc_core_args(parser):