From 3978af9c391cc8a223cee7cb5d5af1e1517b9c7b Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 16 Apr 2024 11:12:30 +0200 Subject: [PATCH] test/test_hyperbus: Update. --- test/test_hyperbus.py | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/test/test_hyperbus.py b/test/test_hyperbus.py index 9a4bf5cfc..e52ca3033 100644 --- a/test/test_hyperbus.py +++ b/test/test_hyperbus.py @@ -56,7 +56,7 @@ class TestHyperBus(unittest.TestCase): self.assertEqual(c2bool(rwds_o[i]), (yield dut.pads.rwds.o)) yield - dut = HyperRAM(HyperRamPads(), latency=5) + dut = HyperRAM(HyperRamPads(), latency=5, latency_mode="fixed") run_simulation(dut, [fpga_gen(dut), hyperram_gen(dut)], vcd_name="sim.vcd") def test_hyperram_write_latency_6_2x(self): @@ -82,7 +82,7 @@ class TestHyperBus(unittest.TestCase): self.assertEqual(c2bool(rwds_o[i]), (yield dut.pads.rwds.o)) yield - dut = HyperRAM(HyperRamPads(), latency=6) + dut = HyperRAM(HyperRamPads(), latency=6, latency_mode="fixed") run_simulation(dut, [fpga_gen(dut), hyperram_gen(dut)], vcd_name="sim.vcd") def test_hyperram_write_latency_7_2x(self): @@ -108,7 +108,7 @@ class TestHyperBus(unittest.TestCase): self.assertEqual(c2bool(rwds_o[i]), (yield dut.pads.rwds.o)) yield - dut = HyperRAM(HyperRamPads(), latency=7) + dut = HyperRAM(HyperRamPads(), latency=7, latency_mode="fixed") run_simulation(dut, [fpga_gen(dut), hyperram_gen(dut)], vcd_name="sim.vcd") def test_hyperram_write_latency_7_1x(self): @@ -162,7 +162,7 @@ class TestHyperBus(unittest.TestCase): self.assertEqual(c2bool(rwds_oe[i]), (yield dut.pads.rwds.oe)) yield - dut = HyperRAM(HyperRamPads(), latency=5) + dut = HyperRAM(HyperRamPads(), latency=5, latency_mode="fixed") run_simulation(dut, [fpga_gen(dut), hyperram_gen(dut)], vcd_name="sim.vcd") def test_hyperram_read_latency_6_2x(self): @@ -190,7 +190,7 @@ class TestHyperBus(unittest.TestCase): self.assertEqual(c2bool(rwds_oe[i]), (yield dut.pads.rwds.oe)) yield - dut = HyperRAM(HyperRamPads(), latency=6) + dut = HyperRAM(HyperRamPads(), latency=6, latency_mode="fixed") run_simulation(dut, [fpga_gen(dut), hyperram_gen(dut)], vcd_name="sim.vcd") def test_hyperram_read_latency_7_2x(self): @@ -218,7 +218,7 @@ class TestHyperBus(unittest.TestCase): self.assertEqual(c2bool(rwds_oe[i]), (yield dut.pads.rwds.oe)) yield - dut = HyperRAM(HyperRamPads(), latency=7) + dut = HyperRAM(HyperRamPads(), latency=7, latency_mode="fixed") run_simulation(dut, [fpga_gen(dut), hyperram_gen(dut)], vcd_name="sim.vcd") def test_hyperram_read_latency_7_1x(self):