From 399b65fa1739916f97b7ce28be585cb3c7eed1ca Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Tue, 11 Feb 2020 16:55:37 +0100
Subject: [PATCH] soc/add_uart: fix bridge
---
litex/soc/integration/soc.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index 42eab475c..c448ebf86 100755
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -876,7 +876,7 @@ class LiteXSoC(SoC):
pads = self.platform.request("serial"),
clk_freq = self.sys_clk_freq,
baudrate = baudrate)
- self.bus.master(name="uart_bridge", master=self.uart.wishbone)
+ self.bus.add_master(name="uart_bridge", master=self.uart.wishbone)
elif name == "crossover":
self.submodules.uart = uart.UARTCrossover()
else: