diff --git a/litex/soc/cores/spi/spi_bone.py b/litex/soc/cores/spi/spi_bone.py
index 11506c72f..e0df08e20 100644
--- a/litex/soc/cores/spi/spi_bone.py
+++ b/litex/soc/cores/spi/spi_bone.py
@@ -9,6 +9,8 @@ from migen import *
 from migen.fhdl.specials import Tristate, TSTriple
 from migen.genlib.cdc import MultiReg
 
+from litex.gen import *
+
 from litex.soc.integration.doc import ModuleDoc, AutoDoc
 from litex.soc.interconnect import wishbone, stream
 
@@ -117,7 +119,7 @@ class SPI2WireDocumentation(ModuleDoc):
 
 # SPIBone Core -------------------------------------------------------------------------------------
 
-class SPIBone(Module, ModuleDoc, AutoDoc):
+class SPIBone(LiteXModule, ModuleDoc):
     """Wishbone Bridge over SPI
 
     This module allows for accessing a Wishbone bridge over a {}-wire protocol.
diff --git a/litex/soc/cores/spi/spi_master.py b/litex/soc/cores/spi/spi_master.py
index 6a0763af4..377cb4782 100644
--- a/litex/soc/cores/spi/spi_master.py
+++ b/litex/soc/cores/spi/spi_master.py
@@ -9,11 +9,13 @@ import math
 from migen import *
 from migen.genlib.cdc import MultiReg
 
+from litex.gen import *
+
 from litex.soc.interconnect.csr import *
 
 # SPI Master ---------------------------------------------------------------------------------------
 
-class SPIMaster(Module, AutoCSR):
+class SPIMaster(LiteXModule):
     """4-wire SPI Master
 
     Provides a simple and minimal hardware SPI Master with CPOL=0, CPHA=0 and build time
@@ -70,7 +72,7 @@ class SPIMaster(Module, AutoCSR):
         ]
 
         # Control FSM ------------------------------------------------------------------------------
-        self.submodules.fsm = fsm = FSM(reset_state="IDLE")
+        self.fsm = fsm = FSM(reset_state="IDLE")
         fsm.act("IDLE",
             self.done.eq(1),
             If(self.start,
diff --git a/litex/soc/cores/spi/spi_slave.py b/litex/soc/cores/spi/spi_slave.py
index 6dfa03323..2b7c4564a 100644
--- a/litex/soc/cores/spi/spi_slave.py
+++ b/litex/soc/cores/spi/spi_slave.py
@@ -9,6 +9,8 @@ import math
 from migen import *
 from migen.genlib.cdc import MultiReg
 
+from litex.gen import *
+
 from litex.soc.interconnect.csr import *
 
 # SPI Slave ----------------------------------------------------------------------------------------
@@ -60,7 +62,7 @@ class SPISlave(Module):
         self.comb += clk_fall.eq(~clk & clk_d)
 
         # Control FSM ------------------------------------------------------------------------------
-        self.submodules.fsm = fsm = FSM(reset_state="IDLE")
+        self.fsm = fsm = FSM(reset_state="IDLE")
         fsm.act("IDLE",
             If(cs,
                 self.start.eq(1),