From 3a2586c48b276b66b7d92037c12c0d9e2aff8836 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 12 Jul 2023 19:42:54 +0200 Subject: [PATCH] soc/add_pcie: Remove csr_ordering parameter (not useful and remove on litepcie). --- litex/soc/integration/soc.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index 54fbd792d..ed7cd4b5c 100644 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -2012,7 +2012,7 @@ class LiteXSoC(SoC): if msi_type == "msi-multi-vector": msi = LitePCIeMSIMultiVector(width=msi_width) if msi_type == "msi-x": - msi = LitePCIeMSIX(endpoint=self.pcie_endpoint, width=msi_width, csr_ordering=self.csr.ordering) + msi = LitePCIeMSIX(endpoint=self.pcie_endpoint, width=msi_width) self.add_module(name=f"{name}_msi", module=msi) # FIXME: On Ultrascale/Ultrascale+ limit rate of IRQs to 1MHz (to prevent issue with # IRQs stalled).