From 5ff23066b7a5c105c8d4c530883ebc502d5139aa Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Thu, 3 Nov 2022 20:20:52 +0800 Subject: [PATCH 1/2] integration/common/get_mem_data: add support for wider data widths Currently the code only supports 32/64 bit SoC data width. Add support for any possible data width that is multiply of 32-bit. Signed-off-by: Icenowy Zheng --- litex/soc/integration/common.py | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/litex/soc/integration/common.py b/litex/soc/integration/common.py index 00e572b43..e15a0f38e 100644 --- a/litex/soc/integration/common.py +++ b/litex/soc/integration/common.py @@ -40,7 +40,7 @@ def get_mem_regions(filename_or_regions, offset): return regions def get_mem_data(filename_or_regions, data_width=32, endianness="big", mem_size=None, offset=0): - assert data_width in [32, 64] + assert data_width % 32 == 0 assert endianness in ["big", "little"] # Return empty list if no filename or regions. @@ -80,11 +80,11 @@ def get_mem_data(filename_or_regions, data_width=32, endianness="big", mem_size= "little": "I" }[endianness] - if data_width == 32: - data[(base - offset)//bytes_per_data + i] = struct.unpack(unpack_order, w)[0] - if data_width == 64: - data[(base - offset)//bytes_per_data + i] = (struct.unpack(unpack_order, w[0:4])[0] << 0) - data[(base - offset)//bytes_per_data + i] |= (struct.unpack(unpack_order, w[4:8])[0] << 32) + data[(base - offset)//bytes_per_data + i] = 0 + for filled_data_width in range(0, data_width, 32): + cur_byte = filled_data_width//8 + data[(base - offset)//bytes_per_data + i] |= (struct.unpack(unpack_order, w[cur_byte:cur_byte+4])[0] << filled_data_width) + filled_data_width += 32 i += 1 return data From 879f1b38bca3a209cd73c187749490d1e3a592aa Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Thu, 3 Nov 2022 20:22:15 +0800 Subject: [PATCH 2/2] integration/soc/add_sdram: connect to main bus with its data width Currently we create a 32-bit Wishbone bus, connect LiteDRAM to it and then connect it to the main SoC bus. This prevents us from getting optimized performance from a wider main bus. Make the intermediate bus to have the same width with the main bus. Signed-off-by: Icenowy Zheng --- litex/soc/integration/soc.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index 65dbbdd3e..e01fba996 100755 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -1581,7 +1581,7 @@ class LiteXSoC(SoC): port.data_width = 2**int(log2(port.data_width)) # Round to nearest power of 2. # Create Wishbone Slave. - wb_sdram = wishbone.Interface() + wb_sdram = wishbone.Interface(data_width=self.bus.data_width) self.bus.add_slave("main_ram", wb_sdram) # L2 Cache