From 3a890a077b138d674f11841564db2042f6871827 Mon Sep 17 00:00:00 2001 From: Andrew Dennison Date: Thu, 1 Feb 2024 10:14:20 +1100 Subject: [PATCH] software/liblitespi/spiflash: fix clk_freq tuning with L2 cache Correct CRC was always calculated, regardless of divisor, as the test flash block was in the L2 cache. This resulted in the minimum divisor being used and incorrect flash reads with 200MHz sys_clock. --- litex/soc/software/liblitespi/spiflash.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/litex/soc/software/liblitespi/spiflash.c b/litex/soc/software/liblitespi/spiflash.c index e31f21410..987b7493e 100644 --- a/litex/soc/software/liblitespi/spiflash.c +++ b/litex/soc/software/liblitespi/spiflash.c @@ -25,6 +25,8 @@ int spiflash_freq_init(void) unsigned int lowest_div, crc, crc_test; lowest_div = spiflash_phy_clk_divisor_read(); + flush_cpu_dcache(); + flush_l2_cache(); crc = crc32((unsigned char *)SPIFLASH_BASE, SPI_FLASH_BLOCK_SIZE); crc_test = crc; @@ -40,6 +42,8 @@ int spiflash_freq_init(void) while((crc == crc_test) && (lowest_div-- > 0)) { spiflash_phy_clk_divisor_write((uint32_t)lowest_div); + flush_cpu_dcache(); + flush_l2_cache(); crc_test = crc32((unsigned char *)SPIFLASH_BASE, SPI_FLASH_BLOCK_SIZE); #ifdef SPIFLASH_DEBUG printf("[DIV: %d] %08x\n\r", lowest_div, crc_test);