From 3ae3d66c80b7010e81cc9c27944c54143d894f4d Mon Sep 17 00:00:00 2001 From: gatecat Date: Tue, 14 Mar 2023 13:03:16 +0100 Subject: [PATCH] cva6_wrapper: Fix reset logic Without this, reset was never being asserted which caused problems on hardware (probably because the CPU started running while the rest of the SoC had reset asserted...) Signed-off-by: gatecat --- litex/soc/cores/cpu/cva6/cva6_wrapper/cva6_wrapper.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/soc/cores/cpu/cva6/cva6_wrapper/cva6_wrapper.sv b/litex/soc/cores/cpu/cva6/cva6_wrapper/cva6_wrapper.sv index 354ed3b67..ded538b71 100644 --- a/litex/soc/cores/cpu/cva6/cva6_wrapper/cva6_wrapper.sv +++ b/litex/soc/cores/cpu/cva6/cva6_wrapper/cva6_wrapper.sv @@ -140,7 +140,7 @@ logic [1:0] irq; assign test_en = 1'b0; always @(posedge clk_i) - ndmreset_n <= ~ndmreset || rst_n; + ndmreset_n <= ~ndmreset && rst_n; // --------------- // AXI Xbar