From 3b00a7c4fe5ece9048f5db4c97c994bf9d50c86b Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 12 Feb 2021 13:40:11 +0100 Subject: [PATCH] README: Add link to the Wiki in the Welcome section. --- README.md | 2 ++ 1 file changed, 2 insertions(+) diff --git a/README.md b/README.md index f45786d19..689f24572 100644 --- a/README.md +++ b/README.md @@ -14,6 +14,8 @@ The common components of a SoC are provided directly: Buses and Streams (Wishbon Think of Migen as a toolbox to create FPGA designs in Python and LiteX as a SoC builder to create/develop/debug FPGA SoCs in Python. +**Want to get started and/or looking for documentation? Make sure to visit the [Wiki](https://github.com/enjoy-digital/litex/wiki)!** + **A question or want to get in touch? Our IRC channel is [#litex at freenode.net](https://webchat.freenode.net/?channels=litex)** # Typical LiteX design flow: