From 3ba7c29ed9468a04583889d2707f6f273fbe1d27 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 7 Feb 2020 19:09:54 +0100 Subject: [PATCH] soc: add add_constant/add_config methods --- litex/soc/integration/common.py | 15 --------------- litex/soc/integration/soc.py | 26 +++++++++++++++++++++++--- litex/soc/integration/soc_core.py | 26 +++++++++----------------- 3 files changed, 32 insertions(+), 35 deletions(-) diff --git a/litex/soc/integration/common.py b/litex/soc/integration/common.py index 695e56090..91811f31f 100644 --- a/litex/soc/integration/common.py +++ b/litex/soc/integration/common.py @@ -73,21 +73,6 @@ def get_mem_data(filename_or_regions, endianness="big", mem_size=None): # SoC primitives ----------------------------------------------------------------------------------- -def SoCConstant(value): - return value - -class SoCMemRegion: - def __init__(self, origin, length, type): - assert type in ["cached", "io", "cached+linker", "io+linker"] - self.origin = origin - self.length = length - self.type = type - - def __str__(self): - return "".format( - self.origin, self.length, self.type) - - class SoCCSRRegion: def __init__(self, origin, busword, obj): self.origin = origin diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index 883fec942..3667a6cbb 100755 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -40,6 +40,11 @@ def build_time(with_time=True): fmt = "%Y-%m-%d %H:%M:%S" if with_time else "%Y-%m-%d" return datetime.datetime.fromtimestamp(time.time()).strftime("%Y-%m-%d %H:%M:%S") +# SoCConstant -------------------------------------------------------------------------------------- + +def SoCConstant(value): + return value + # SoCRegion ---------------------------------------------------------------------------------------- class SoCRegion: @@ -514,6 +519,9 @@ class SoC(Module): self.logger.info(colorer("Creating new SoC... ({})".format(build_time()), color="cyan")) self.logger.info(colorer("-"*80, color="bright")) + # SoC attributes --------------------------------------------------------------------------- + self.constants = {} + # SoC Bus Handler -------------------------------------------------------------------------- self.submodules.bus = SoCBusHandler( standard = bus_standard, @@ -553,6 +561,20 @@ class SoC(Module): self.logger.error("{} SubModule already declared.".format(colorer(name, "red"))) raise + def add_constant(self, name, value=None): + name = name.upper() + if name in self.constants.keys(): + self.logger.error("{} Constant already declared.".format(colorer(name, "red"))) + raise + self.constants[name] = SoCConstant(value) + + def add_config(self, name, value): + name = "CONFIG_" + name + if isinstance(value, str): + self.add_constant(name + "_" + value) + else: + self.add_constant(name, value) + # SoC Main components -------------------------------------------------------------------------- def add_ram(self, name, origin, size, contents=[], mode="rw"): ram_bus = wishbone.Interface(data_width=self.bus.data_width) @@ -561,7 +583,7 @@ class SoC(Module): self.check_if_exists(name) self.logger.info("RAM {} {} {}.".format( colorer(name), - colorer("added", "green"), + colorer("added", color="green"), self.bus.regions[name])) setattr(self.submodules, name, ram) @@ -614,8 +636,6 @@ class SoC(Module): register = True, timeout_cycles = self.bus.timeout) - #exit() - # Test (FIXME: move to litex/text and improve) ----------------------------------------------------- if __name__ == "__main__": diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py index 8d6398ecc..044503810 100644 --- a/litex/soc/integration/soc_core.py +++ b/litex/soc/integration/soc_core.py @@ -24,7 +24,7 @@ from litex.soc.cores import identifier, timer, uart from litex.soc.cores import cpu from litex.soc.interconnect import wishbone, csr_bus, wishbone2csr from litex.soc.integration.common import * -from litex.soc.integration.soc import SoCRegion, SoC, SoCController +from litex.soc.integration.soc import SoCConstant, SoCRegion, SoC, SoCController __all__ = [ "mem_decoder", @@ -100,7 +100,6 @@ class SoCCore(SoC): # SoC's Config/Constants/Regions self.config = {} - self.constants = {} self.csr_regions = {} # CSR masters list @@ -135,10 +134,10 @@ class SoCCore(SoC): self.add_controller("ctrl") # Add CPU - self.config["CPU_TYPE"] = str(cpu_type).upper() + self.add_config("CPU_TYPE", str(cpu_type).upper()) if cpu_type is not None: if cpu_variant is not None: - self.config["CPU_VARIANT"] = str(cpu_variant.split('+')[0]).upper() + self.add_config("CPU_VARIANT", str(cpu_variant.split('+')[0])) # Check type if cpu_type not in cpu.CPUS.keys(): @@ -159,7 +158,7 @@ class SoCCore(SoC): # Set reset address self.cpu.set_reset_address(self.soc_mem_map["rom"] if integrated_rom_size else cpu_reset_address) - self.config["CPU_RESET_ADDR"] = self.cpu.reset_address + self.add_config("CPU_RESET_ADDR", self.cpu.reset_address) # Add CPU buses as 32-bit Wishbone masters for cpu_bus in self.cpu.buses: @@ -224,15 +223,15 @@ class SoCCore(SoC): self.add_csr("uart", use_loc_if_exists=True) self.add_interrupt("uart", use_loc_if_exists=True) - self.config["CLOCK_FREQUENCY"] = int(clk_freq) + self.add_config("CLOCK_FREQUENCY", int(clk_freq)) # Add Timer if with_timer: self.add_timer(name="timer0") # Add Wishbone to CSR bridge - self.config["CSR_DATA_WIDTH"] = csr_data_width - self.config["CSR_ALIGNMENT"] = csr_alignment + self.add_config("CSR_DATA_WIDTH", csr_data_width) + self.add_config("CSR_ALIGNMENT", csr_alignment) if with_wishbone: self.add_csr_bridge(self.soc_mem_map["csr"]) self.add_csr_master(self.csr_bridge.csr) # FIXME @@ -293,11 +292,6 @@ class SoCCore(SoC): self.check_io_region(name, origin, 0x800) self.csr_regions[name] = SoCCSRRegion(origin, busword, obj) - def add_constant(self, name, value=None): - if name in self.constants.keys(): - raise ValueError("Constant {} already declared.".format(name)) - self.constants[name] = SoCConstant(value) - def get_csr_dev_address(self, name, memory): if memory is not None: name = name + "_" + memory.name_override @@ -366,10 +360,8 @@ class SoCCore(SoC): # Add CSRs / Config items to constants for name, constant in self.csrbankarray.constants: self.add_constant(name.upper() + "_" + constant.name.upper(), constant.value.value) - for name, value in sorted(self.config.items(), key=itemgetter(0)): - self.add_constant("CONFIG_" + name.upper(), value) - if isinstance(value, str): - self.add_constant("CONFIG_" + name.upper() + "_" + value) + for name, value in self.config.items(): + self.add_config(name, value) # Connect interrupts if hasattr(self.cpu, "interrupt"):