From 3bf5c1192898b6a1f1f92335eeb5d8857571f9dc Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Tue, 24 May 2022 16:20:37 +0200
Subject: [PATCH] build/osfpga: Add test_soc.py to test simple SoC builds.

---
 litex/build/osfpga/test_soc.py | 64 ++++++++++++++++++++++++++++++++++
 1 file changed, 64 insertions(+)
 create mode 100755 litex/build/osfpga/test_soc.py

diff --git a/litex/build/osfpga/test_soc.py b/litex/build/osfpga/test_soc.py
new file mode 100755
index 000000000..3c5fd4822
--- /dev/null
+++ b/litex/build/osfpga/test_soc.py
@@ -0,0 +1,64 @@
+#!/usr/bin/env python3
+
+#
+# This file is part of LiteX.
+#
+# Copyright (c) 2022 Florent Kermarrec <florent@enjoy-digital.fr>
+# SPDX-License-Identifier: BSD-2-Clause
+
+from migen import *
+
+from litex.build.io import CRG
+from litex.build.generic_platform import Pins, Subsignal
+from litex.build.osfpga import OSFPGAPlatform
+
+from litex.soc.integration.soc_core import *
+from litex.soc.integration.builder import *
+
+# Platform ---------------------------------------------------------------------------------
+
+_io = [
+    # Clk.
+    ("clk", 0, Pins(1)),
+
+    # Serial.
+    ("serial", 0,
+        Subsignal("tx", Pins(1)),
+        Subsignal("rx", Pins(1)),
+    ),
+]
+
+class Platform(OSFPGAPlatform):
+    def __init__(self, toolchain="foedag"):
+        OSFPGAPlatform.__init__(self, device="test", toolchain=toolchain, io=_io)
+
+# BaseSoC ------------------------------------------------------------------------------------------
+
+class BaseSoC(SoCCore):
+    def __init__(self, platform, sys_clk_freq=int(10e6), **kwargs):
+        # CRG --------------------------------------------------------------------------------------
+        self.submodules.crg = CRG(platform.request("clk"))
+
+        # SoCCore ----------------------------------------------------------------------------------
+        SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX Test SoC on OS-FPGA", **kwargs)
+
+# Build --------------------------------------------------------------------------------------------
+
+def main():
+    from litex.soc.integration.soc import LiteXSoCArgumentParser
+    parser = LiteXSoCArgumentParser(description="LiteX Test SoC on OS-FPGA")
+    target_group = parser.add_argument_group(title="Target options")
+    target_group.add_argument("--build",     action="store_true", help="Build design.")
+    target_group.add_argument("--toolchain", default="foedag",    help="FPGA toolchain.")
+    builder_args(parser)
+    soc_core_args(parser)
+    args = parser.parse_args()
+
+    platform = Platform(toolchain=args.toolchain)
+    soc      = BaseSoC(platform,**soc_core_argdict(args))
+    builder  = Builder(soc, **builder_argdict(args))
+    if args.build:
+        builder.build()
+
+if __name__ == "__main__":
+    main()