diff --git a/litex/soc/cores/dma.py b/litex/soc/cores/dma.py
index e45bf4400..a6df58700 100644
--- a/litex/soc/cores/dma.py
+++ b/litex/soc/cores/dma.py
@@ -155,7 +155,7 @@ class WishboneDMAWriter(Module, AutoCSR):
         if with_csr:
             self.add_csr()
 
-    def add_csr(self, default_base=0, default_length=0, default_enable=0, default_loop=0):
+    def add_csr(self, default_base=0, default_length=0, default_enable=0, default_loop=0, ready_on_idle=1):
         self._sink = self.sink
         self.sink  = stream.Endpoint([("data", self.bus.data_width)])
 
@@ -182,6 +182,7 @@ class WishboneDMAWriter(Module, AutoCSR):
         self.submodules += fsm
         self.comb += fsm.reset.eq(~self._enable.storage)
         fsm.act("IDLE",
+            self.sink.ready.eq(ready_on_idle),
             NextValue(offset, 0),
             NextState("RUN"),
         )