From 3cf612666383522dce1fd3a9fccdbe281baec82a Mon Sep 17 00:00:00 2001 From: Pawel Sagan Date: Wed, 1 Sep 2021 16:54:53 +0200 Subject: [PATCH] litex: adding explicit clk signal to ODDR/IDDR models in DDRTristate --- litex/build/xilinx/common.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/litex/build/xilinx/common.py b/litex/build/xilinx/common.py index 2de19bac7..f16e3454a 100644 --- a/litex/build/xilinx/common.py +++ b/litex/build/xilinx/common.py @@ -159,9 +159,9 @@ class XilinxDDRTristateImpl(Module): _o = Signal() _oe_n = Signal() _i = Signal() - self.specials += DDROutput(i1, i2, _o) - self.specials += DDROutput(~oe1, ~oe2, _oe_n) - self.specials += DDRInput(_i, o1, o2) + self.specials += DDROutput(i1, i2, _o, clk) + self.specials += DDROutput(~oe1, ~oe2, _oe_n, clk) + self.specials += DDRInput(_i, o1, o2, clk) self.specials += Instance("IOBUF", io_IO = io, o_O = _i,