From 3d530e0b59fbee8a0d60be14fe9e118350015cc6 Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Sat, 22 Jun 2024 17:54:41 +0100 Subject: [PATCH] integration/soc: data_width_convert: Inherit more bus properties For data_width converter we need to ensure that adapted interface have same properties as it's parent interface, so that id and user signals for AXI will be propagated properly from parent to adapted interface. Signed-off-by: Jiaxun Yang --- litex/soc/integration/soc.py | 23 ++++++++++++++++++----- 1 file changed, 18 insertions(+), 5 deletions(-) diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index 85b0360c3..4198bb453 100644 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -346,11 +346,24 @@ class SoCBusHandler(LiteXModule): axi.AXILiteInterface : axi.AXILiteConverter, axi.AXIInterface : axi.AXIConverter, }[interface_cls] - adapted_interface = interface_cls( - data_width = self.data_width, - address_width = self.address_width, - addressing = interface.addressing, - ) + args = { + 'data_width': self.data_width, + 'address_width': self.address_width, + 'addressing': interface.addressing, + 'bursting' : interface.bursting, + } + if isinstance(interface, axi.AXIInterface): + args.update({ + 'version' : interface.version, + 'id_width': interface.id_width, + 'aw_user_width': interface.aw.user_width, + 'w_user_width': interface.w.user_width, + 'b_user_width': interface.b.user_width, + 'ar_user_width': interface.ar.user_width, + 'r_user_width': interface.r.user_width, + }) + adapted_interface = interface_cls(**args) + if direction == "m2s": master, slave = interface, adapted_interface elif direction == "s2m":