diff --git a/litex/boards/targets/de0nano.py b/litex/boards/targets/de0nano.py
index 63ac8f8fa..7fb9d6258 100755
--- a/litex/boards/targets/de0nano.py
+++ b/litex/boards/targets/de0nano.py
@@ -98,8 +98,9 @@ class BaseSoC(SoCSDRAM):
         if not self.integrated_main_ram_size:
             self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"),)
             sdram_module = IS42S16160(self.clk_freq, "1:1")
-            self.register_sdram(self.sdrphy, "minicon",
-                                sdram_module.geom_settings, sdram_module.timing_settings)
+            self.register_sdram(self.sdrphy,
+                                sdram_module.geom_settings,
+                                sdram_module.timing_settings)
 
 def main():
     parser = argparse.ArgumentParser(description="LiteX SoC port to the Altera DE0 Nano")
diff --git a/litex/boards/targets/kc705.py b/litex/boards/targets/kc705.py
index 14c8696c5..65500af7c 100755
--- a/litex/boards/targets/kc705.py
+++ b/litex/boards/targets/kc705.py
@@ -84,7 +84,7 @@ class BaseSoC(SoCSDRAM):
     }
     csr_map.update(SoCSDRAM.csr_map)
 
-    def __init__(self, toolchain="ise", sdram_controller_type="minicon", **kwargs):
+    def __init__(self, toolchain="ise", **kwargs):
         platform = kc705.Platform(toolchain=toolchain)
         SoCSDRAM.__init__(self, platform,
                           clk_freq=125*1000000, cpu_reset_address=0xaf0000,
@@ -95,7 +95,7 @@ class BaseSoC(SoCSDRAM):
         if not self.integrated_main_ram_size:
             self.submodules.ddrphy = k7ddrphy.K7DDRPHY(platform.request("ddram"))
             sdram_module = MT8JTF12864(self.clk_freq, "1:4")
-            self.register_sdram(self.ddrphy, sdram_controller_type,
+            self.register_sdram(self.ddrphy,
                                 sdram_module.geom_settings, sdram_module.timing_settings)
 
         if not self.integrated_rom_size:
diff --git a/litex/boards/targets/minispartan6.py b/litex/boards/targets/minispartan6.py
index 082441db9..04443bdea 100755
--- a/litex/boards/targets/minispartan6.py
+++ b/litex/boards/targets/minispartan6.py
@@ -78,8 +78,9 @@ class BaseSoC(SoCSDRAM):
         if not self.integrated_main_ram_size:
             self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
             sdram_module = AS4C16M16(clk_freq, "1:1")
-            self.register_sdram(self.sdrphy, "minicon",
-                                sdram_module.geom_settings, sdram_module.timing_settings)
+            self.register_sdram(self.sdrphy,
+                                sdram_module.geom_settings,
+                                sdram_module.timing_settings)
 
 
 def main():
diff --git a/litex/boards/targets/sim.py b/litex/boards/targets/sim.py
index ecc5c7c1f..b18996eaf 100755
--- a/litex/boards/targets/sim.py
+++ b/litex/boards/targets/sim.py
@@ -46,8 +46,9 @@ class BaseSoC(SoCSDRAM):
                 write_latency=0
             )
             self.submodules.sdrphy = SDRAMPHYModel(sdram_module, phy_settings)
-            self.register_sdram(self.sdrphy, "minicon",
-                                sdram_module.geom_settings, sdram_module.timing_settings)
+            self.register_sdram(self.sdrphy,
+                                sdram_module.geom_settings,
+                                sdram_module.timing_settings)
             # reduce memtest size to speed up simulation
             self.add_constant("MEMTEST_DATA_SIZE", 8*1024)
             self.add_constant("MEMTEST_ADDR_SIZE", 8*1024)