From 3d98be0997f07a8f11cfa234d785d79adea02d92 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 21 Apr 2016 09:39:21 +0200 Subject: [PATCH] use new Record.connect omit parameter (replace leave_out) --- litex/soc/cores/sdram/phy/s6ddrphy.py | 10 +++++----- litex/soc/interconnect/stream.py | 2 +- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/litex/soc/cores/sdram/phy/s6ddrphy.py b/litex/soc/cores/sdram/phy/s6ddrphy.py index 71148bb6a..8fe77a53c 100644 --- a/litex/soc/cores/sdram/phy/s6ddrphy.py +++ b/litex/soc/cores/sdram/phy/s6ddrphy.py @@ -451,14 +451,14 @@ class S6QuarterRateDDRPHY(Module): # DFI adaptation # Commands and writes - dfi_leave_out = set(["rddata", "rddata_valid", "wrdata_en"]) + dfi_omit = set(["rddata", "rddata_valid", "wrdata_en"]) self.comb += [ If(~phase_sel, - self.dfi.phases[0].connect(half_rate_phy.dfi.phases[0], leave_out=dfi_leave_out), - self.dfi.phases[1].connect(half_rate_phy.dfi.phases[1], leave_out=dfi_leave_out), + self.dfi.phases[0].connect(half_rate_phy.dfi.phases[0], omit=dfi_omit), + self.dfi.phases[1].connect(half_rate_phy.dfi.phases[1], omit=dfi_omit), ).Else( - self.dfi.phases[2].connect(half_rate_phy.dfi.phases[0], leave_out=dfi_leave_out), - self.dfi.phases[3].connect(half_rate_phy.dfi.phases[1], leave_out=dfi_leave_out), + self.dfi.phases[2].connect(half_rate_phy.dfi.phases[0], omit=dfi_omit), + self.dfi.phases[3].connect(half_rate_phy.dfi.phases[1], omit=dfi_omit), ), ] wr_data_en = self.dfi.phases[self.settings.wrphase].wrdata_en & ~phase_sel diff --git a/litex/soc/interconnect/stream.py b/litex/soc/interconnect/stream.py index a12562fd8..63f4c1f68 100644 --- a/litex/soc/interconnect/stream.py +++ b/litex/soc/interconnect/stream.py @@ -276,7 +276,7 @@ class Converter(Module): else: self.source = Endpoint([("data", nbits_to)]) self.comb += converter.source.connect(self.source, - leave_out=set(["valid_token_count"])) + omit=set(["valid_token_count"])) class StrideConverter(Module):