From 23a0d8fa2aa0255c4101550f6c18152f36d565f4 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 26 Jun 2024 16:06:42 +0200 Subject: [PATCH 1/3] soc/cores/dma/WishboneDMAReader: Split add_csr() in add_ctrl() /add_csr() since in some case just want to control the module from signals/user logic. --- litex/soc/cores/dma.py | 48 ++++++++++++++++++++++++++++++------------ 1 file changed, 35 insertions(+), 13 deletions(-) diff --git a/litex/soc/cores/dma.py b/litex/soc/cores/dma.py index 735d102e6..94f081381 100644 --- a/litex/soc/cores/dma.py +++ b/litex/soc/cores/dma.py @@ -71,15 +71,16 @@ class WishboneDMAReader(LiteXModule): # CSRs. if with_csr: + self.add_ctrl() self.add_csr() - def add_csr(self, default_base=0, default_length=0, default_enable=0, default_loop=0): - self._base = CSRStorage(64, reset=default_base) - self._length = CSRStorage(32, reset=default_length) - self._enable = CSRStorage(reset=default_enable) - self._done = CSRStatus() - self._loop = CSRStorage(reset=default_loop) - self._offset = CSRStatus(32) + def add_ctrl(self): + self.base = Signal(64) + self.length = Signal(32) + self.enable = Signal() + self.done = Signal() + self.loop = Signal() + self.offset = Signal(32) # # # @@ -87,13 +88,13 @@ class WishboneDMAReader(LiteXModule): base = Signal(self.bus.adr_width) offset = Signal(self.bus.adr_width) length = Signal(self.bus.adr_width) - self.comb += base.eq(self._base.storage[shift:]) - self.comb += length.eq(self._length.storage[shift:]) + self.comb += base.eq(self.base[shift:]) + self.comb += length.eq(self.length[shift:]) - self.comb += self._offset.status.eq(offset) + self.comb += self.offset.eq(offset) self.fsm = fsm = ResetInserter()(FSM(reset_state="IDLE")) - self.comb += fsm.reset.eq(~self._enable.storage) + self.comb += fsm.reset.eq(~self.enable) fsm.act("IDLE", NextValue(offset, 0), NextState("RUN"), @@ -105,7 +106,7 @@ class WishboneDMAReader(LiteXModule): If(self.sink.ready, NextValue(offset, offset + 1), If(self.sink.last, - If(self._loop.storage, + If(self.loop, NextValue(offset, 0) ).Else( NextState("DONE") @@ -113,7 +114,28 @@ class WishboneDMAReader(LiteXModule): ) ) ) - fsm.act("DONE", self._done.status.eq(1)) + fsm.act("DONE", self.done.eq(1)) + + def add_csr(self, default_base=0, default_length=0, default_enable=0, default_loop=0): + self._base = CSRStorage(64, reset=default_base) + self._length = CSRStorage(32, reset=default_length) + self._enable = CSRStorage(reset=default_enable) + self._done = CSRStatus() + self._loop = CSRStorage(reset=default_loop) + self._offset = CSRStatus(32) + + # # # + + self.comb += [ + # Control. + self.base.eq(self._base.storage), + self.length.eq(self._length.storage), + self.enable.eq(self._enable.storage), + self.loop.eq(self._loop.storage), + # Status. + self._done.status.eq(self.done), + self._offset.status.eq(self.offset), + ] # WishboneDMAWriter -------------------------------------------------------------------------------- From 01a15e4bbfb001a541ab5e691767960ea29bc4bb Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 26 Jun 2024 16:13:45 +0200 Subject: [PATCH 2/3] soc/cores/dma/WishboneDMAReader: Split add_csr() in add_ctrl() /add_csr() since in some case just want to control the module from signals/user logic. --- litex/soc/cores/dma.py | 48 ++++++++++++++++++++++++++++++------------ 1 file changed, 35 insertions(+), 13 deletions(-) diff --git a/litex/soc/cores/dma.py b/litex/soc/cores/dma.py index 94f081381..4e14a2563 100644 --- a/litex/soc/cores/dma.py +++ b/litex/soc/cores/dma.py @@ -173,18 +173,19 @@ class WishboneDMAWriter(LiteXModule): # CSRs. if with_csr: + self.add_ctrl() self.add_csr() - def add_csr(self, default_base=0, default_length=0, default_enable=0, default_loop=0, ready_on_idle=1): + def add_ctrl(self, ready_on_idle=1): self._sink = self.sink self.sink = stream.Endpoint([("data", self.bus.data_width)]) - self._base = CSRStorage(64, reset=default_base) - self._length = CSRStorage(32, reset=default_length) - self._enable = CSRStorage(reset=default_enable) - self._done = CSRStatus() - self._loop = CSRStorage(reset=default_loop) - self._offset = CSRStatus(32) + self.base = Signal(64) + self.length = Signal(32) + self.enable = Signal() + self.done = Signal() + self.loop = Signal() + self.offset = Signal(32) # # # @@ -192,13 +193,13 @@ class WishboneDMAWriter(LiteXModule): base = Signal(self.bus.adr_width) offset = Signal(self.bus.adr_width) length = Signal(self.bus.adr_width) - self.comb += base.eq(self._base.storage[shift:]) - self.comb += length.eq(self._length.storage[shift:]) + self.comb += base.eq(self.base[shift:]) + self.comb += length.eq(self.length[shift:]) - self.comb += self._offset.status.eq(offset) + self.comb += self.offset.eq(offset) self.fsm = fsm = ResetInserter()(FSM(reset_state="IDLE")) - self.comb += fsm.reset.eq(~self._enable.storage) + self.comb += fsm.reset.eq(~self.enable) fsm.act("IDLE", self.sink.ready.eq(ready_on_idle), NextValue(offset, 0), @@ -213,7 +214,7 @@ class WishboneDMAWriter(LiteXModule): If(self.sink.valid & self.sink.ready, NextValue(offset, offset + 1), If(self._sink.last, - If(self._loop.storage, + If(self.loop, NextValue(offset, 0) ).Else( NextState("DONE") @@ -221,4 +222,25 @@ class WishboneDMAWriter(LiteXModule): ) ) ) - fsm.act("DONE", self._done.status.eq(1)) + fsm.act("DONE", self.done.eq(1)) + + def add_csr(self, default_base=0, default_length=0, default_enable=0, default_loop=0): + self._base = CSRStorage(64, reset=default_base) + self._length = CSRStorage(32, reset=default_length) + self._enable = CSRStorage(reset=default_enable) + self._done = CSRStatus() + self._loop = CSRStorage(reset=default_loop) + self._offset = CSRStatus(32) + + # # # + + self.comb += [ + # Control. + self.base.eq(self._base.storage), + self.length.eq(self._length.storage), + self.enable.eq(self._enable.storage), + self.loop.eq(self._loop.storage), + # Status. + self._done.status.eq(self.done), + self._offset.status.eq(self.offset), + ] From 4b745f9eba1b4d01e3d0b5132e8205b392c197de Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 26 Jun 2024 17:57:47 +0200 Subject: [PATCH 3/3] soc/cores/dma: Add default parameters to add_ctrl. --- litex/soc/cores/dma.py | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/litex/soc/cores/dma.py b/litex/soc/cores/dma.py index 4e14a2563..7bd451a00 100644 --- a/litex/soc/cores/dma.py +++ b/litex/soc/cores/dma.py @@ -74,12 +74,12 @@ class WishboneDMAReader(LiteXModule): self.add_ctrl() self.add_csr() - def add_ctrl(self): - self.base = Signal(64) - self.length = Signal(32) - self.enable = Signal() + def add_ctrl(self, default_base=0, default_length=0, default_enable=0, default_loop=0): + self.base = Signal(64, reset=default_base) + self.length = Signal(32, reset=default_length) + self.enable = Signal(reset=default_enable) self.done = Signal() - self.loop = Signal() + self.loop = Signal(reset=default_loop) self.offset = Signal(32) # # # @@ -176,15 +176,15 @@ class WishboneDMAWriter(LiteXModule): self.add_ctrl() self.add_csr() - def add_ctrl(self, ready_on_idle=1): + def add_ctrl(self, default_base=0, default_length=0, default_enable=0, default_loop=0, ready_on_idle=1): self._sink = self.sink self.sink = stream.Endpoint([("data", self.bus.data_width)]) - self.base = Signal(64) - self.length = Signal(32) - self.enable = Signal() + self.base = Signal(64, reset=default_base) + self.length = Signal(32, reset=default_length) + self.enable = Signal(reset=default_enable) self.done = Signal() - self.loop = Signal() + self.loop = Signal(reset=default_loop) self.offset = Signal(32) # # #