From 3de5832b9c682add293804459908f1e1f3a92a0f Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Tue, 3 Sep 2024 07:58:24 +0200 Subject: [PATCH] vexiiriscv: Now use pll.locked for debug reset --- litex/soc/cores/cpu/vexiiriscv/core.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/litex/soc/cores/cpu/vexiiriscv/core.py b/litex/soc/cores/cpu/vexiiriscv/core.py index c518ae24f..6bbd42241 100755 --- a/litex/soc/cores/cpu/vexiiriscv/core.py +++ b/litex/soc/cores/cpu/vexiiriscv/core.py @@ -514,10 +514,10 @@ class VexiiRiscv(CPU): if soc.get_build_name() == "sim": self.comb += If(debug_ndmreset_rise, soc.crg.cd_sys.rst.eq(1)) else: - if hasattr(soc.crg, "rst"): + if hasattr(soc.crg.pll, "locked"): + self.comb += If(debug_ndmreset, soc.crg.pll.locked.eq(0)) + elif hasattr(soc.crg, "rst"): self.comb += If(debug_ndmreset_rise, soc.crg.rst.eq(1)) - elif hasattr(soc.crg.pll, "reset"): - self.comb += If(debug_ndmreset_rise, soc.crg.pll.reset.eq(1)) else: raise Exception("Pll has no reset ?")