From 3de5f2049697d1840b5f1bbe853ff17fddab3bef Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 10 Feb 2023 19:08:13 +0100 Subject: [PATCH] build/sim/litex_sim: Only compiles video module when used. Avoid additional SDL2 dependency for regular simulations. --- litex/build/sim/core/Makefile | 4 ++-- litex/build/sim/core/modules/Makefile | 2 +- litex/build/sim/verilator.py | 24 +++++++++++++++++++----- litex/tools/litex_sim.py | 5 ++--- 4 files changed, 24 insertions(+), 11 deletions(-) diff --git a/litex/build/sim/core/Makefile b/litex/build/sim/core/Makefile index 62b7a1f25..4866d3a87 100644 --- a/litex/build/sim/core/Makefile +++ b/litex/build/sim/core/Makefile @@ -10,11 +10,11 @@ ifeq ($(UNAME_S),Darwin) CFLAGS += -I/opt/homebrew/include LDFLAGS += -L/opt/homebrew/lib endif - LDFLAGS += -lpthread -ljson-c -lz -lm -lstdc++ -ldl -levent + LDFLAGS += -lpthread -ljson-c -lz -lm -lstdc++ -ldl -levent $(if $(VIDEO), -lSDL2) else CC ?= gcc CFLAGS += -ggdb - LDFLAGS += -lpthread -Wl,--no-as-needed -ljson-c -lz -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -lSDL2 + LDFLAGS += -lpthread -Wl,--no-as-needed -ljson-c -lz -lm -lstdc++ -Wl,--no-as-needed -ldl -levent $(if $(VIDEO), -lSDL2) endif CFLAGS += -Wall -$(OPT_LEVEL) $(if $(COVERAGE), -DVM_COVERAGE) $(if $(TRACE_FST), -DTRACE_FST) diff --git a/litex/build/sim/core/modules/Makefile b/litex/build/sim/core/modules/Makefile index d46147b34..d300e2367 100644 --- a/litex/build/sim/core/modules/Makefile +++ b/litex/build/sim/core/modules/Makefile @@ -1,5 +1,5 @@ include ../variables.mak -MODULES = xgmii_ethernet ethernet serial2console serial2tcp clocker spdeeprom gmii_ethernet video +MODULES = xgmii_ethernet ethernet serial2console serial2tcp clocker spdeeprom gmii_ethernet $(if $(VIDEO), video) .PHONY: $(MODULES) $(EXTRA_MOD_LIST) all: $(MODULES) $(EXTRA_MOD_LIST) diff --git a/litex/build/sim/verilator.py b/litex/build/sim/verilator.py index 970420aa8..26149bb32 100644 --- a/litex/build/sim/verilator.py +++ b/litex/build/sim/verilator.py @@ -106,7 +106,7 @@ extern "C" void litex_sim_init(void **out) tools.write_to_file("sim_init.cpp", content) -def _generate_sim_variables(include_paths, extra_mods, extra_mods_path): +def _generate_sim_variables(include_paths, extra_mods, extra_mods_path, video): tapcfg_dir = get_data_mod("misc", "tapcfg").data_location include = "" for path in include_paths: @@ -115,7 +115,8 @@ def _generate_sim_variables(include_paths, extra_mods, extra_mods_path): SRC_DIR = {} INC_DIR = {} TAPCFG_DIRECTORY = {} -""".format(core_directory, include, tapcfg_dir) +VIDEO = {} +""".format(core_directory, include, tapcfg_dir, int(video)) if extra_mods: modlist = " ".join(extra_mods) @@ -123,6 +124,7 @@ TAPCFG_DIRECTORY = {} content += "EXTRA_MOD_BASE_DIR = " + extra_mods_path + "\n" tools.write_to_file(extra_mods_path + "/variables.mak", content) + tools.write_to_file("variables.mak", content) @@ -131,7 +133,7 @@ def _generate_sim_config(config): tools.write_to_file("sim_config.js", content) -def _build_sim(build_name, sources, jobs, threads, coverage, opt_level="O3", trace_fst=False): +def _build_sim(build_name, sources, jobs, threads, coverage, opt_level="O3", trace_fst=False, video=False): makefile = os.path.join(core_directory, 'Makefile') cc_srcs = [] @@ -149,6 +151,7 @@ make -C . -f {} {} {} {} {} {} {} "COVERAGE=1" if coverage else "", "OPT_LEVEL={}".format(opt_level), "TRACE_FST=1" if trace_fst else "", + "VIDEO=1" if video else "", ) build_script_file = "build_" + build_name + ".sh" tools.write_to_file(build_script_file, build_script_contents, force_unix=True) @@ -200,6 +203,7 @@ class SimVerilatorToolchain: sim_config = None, coverage = False, opt_level = "O0", + video = False, trace = False, trace_fst = False, trace_start = 0, @@ -237,14 +241,24 @@ class SimVerilatorToolchain: _generate_sim_variables(platform.verilog_include_paths, extra_mods, - extra_mods_path) + extra_mods_path, + video) # Generate sim config if sim_config: _generate_sim_config(sim_config) # Build - _build_sim(build_name, platform.sources, jobs, threads, coverage, opt_level, trace_fst) + _build_sim( + build_name = build_name, + sources = platform.sources, + jobs = jobs, + threads = threads, + coverage = coverage, + opt_level = opt_level, + trace_fst = trace_fst, + video = video, + ) # Run if run: diff --git a/litex/tools/litex_sim.py b/litex/tools/litex_sim.py index 764e5268b..85f8f914a 100755 --- a/litex/tools/litex_sim.py +++ b/litex/tools/litex_sim.py @@ -538,7 +538,7 @@ def main(): # Video. if args.with_video_framebuffer or args.with_video_terminal: - sim_config.add_module("video", "vga") + sim_config.add_module("video", "vga") # SoC ------------------------------------------------------------------------------------------ soc = SimSoC( @@ -574,11 +574,10 @@ def main(): generate_gtkw_savefile(builder, vns, args.trace_fst) builder = Builder(soc, **parser.builder_argdict) - print(parser.builder_argdict) - builder.build( sim_config = sim_config, interactive = not args.non_interactive, + video = args.with_video_framebuffer or args.with_video_terminal, pre_run_callback = pre_run_callback, **parser.toolchain_argdict, )