diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index 1c912e211..4e9a4b87c 100755
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -1461,7 +1461,8 @@ class LiteXSoC(SoC):
 
         # Add SDRAM region.
         main_ram_region = SoCRegion(origin=self.mem_map.get("main_ram", origin), 
-                                    size=sdram_size)
+                                    size=sdram_size,
+                                    mode="rwx")
         self.bus.add_region("main_ram", main_ram_region)
 
         # Add CPU's direct memory buses (if not already declared) ----------------------------------